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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C491/392 486WB PC/AT Chipset <04/21/91
***Info:...
***Configurations:...
***Features:
o 1X clock source, supporting systems running up to 50 Mhz
o two 160-pin CMOS Plastic Flat Package (PFP), and one 84-pin PLCC
o Copy-Back Direct-Mapped Cache with size of 64 KB, 128 KB, 256 KB
and 512 KB
o up to 10% performance enhancement from write-through cache scheme
o supports 2,1,1,1 cache burst cycle as well as 3,1,1,1 cycle
o on-chip comparator determines cache hit or miss
o up to 64-MB of local high-speed, page-mode, DRAM memory space
o burst-line-fill during Cache-Read-Miss
o control of two non-cacheable regions
o shadow RAM support
o optional caching of shadowed Video BIOS
o hidden refresh
o slow refresh available for a laptop application.
o 8042 emulation for fast CPU-reset and gateA20 generation
o turbo/slow speed selection
o AT bus clock selectable from CLKIN/4 or CLKIN/6
o 0 or 1 wait state selectable for 16-bit AT bus cycle
o CAS# before RAS# refresh reduces power consumption
o optional 0 or 1 wait state for Cache-Write-Hit
o WEITEK 4167 coprocessor support
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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*Winbond...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89
***Info:
GENERAL DESCRIPTION
The W860451 is an enhanced version of the popular W860450 asynchronous
communication element (ACE) fabricated using WINBOND'S CMOS process.
The device supports one serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM. and
parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the complete status of the UART at any time
during the functional operation. Status information reported includes
the type and condition of the transfer operations being performed by
the UART as well as any error conditions (parity, overrun, framing. or
break interrupt). The UART includes a programmable baud rate
generator that is capable of dividing the timing reference clock input
by divisors of 1 to (2^16 - 1), and producing a 16x clock for driving
the internal transmitter logic. Provisions are also included to use
this 16x clock to drive the receiver logic. The UART includes a
complete MODEM-control capability and a processor-interrupt system.
interrupts can be programmed to the user’s requirements, minimizing
the computing required to handle the communications link. In addition
to its communication interface capabilities, the W860451 provides the
user with a parallel Centronics type printer.
***Versions:...
***Features:...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
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