[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance  PC/AT platforms.   This chipset will  support 486SX/
DX/DX2/DX4  and P24T microprocessors  in the  most cost  effective and
power  efficient  designs  available  today.  For  power  users,  this
chipset offers optimum performance for systems running up to 50MHz.

Based  fundamentally  on  OPTi's   proven  82C801  and  82C802  design
architectures,  the 82C895 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The  820895  supports the  latest  write-back  processor designs  from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for   compatibility  and   performance.   It  also   includes  an
82C206-compatible  Integrated Peripherals Controller  (IPC). all  in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.

2.1 Power Management

This block diagram [see  datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN  strategy.  System designs  can easily accommodate
both SLe  and non-SLe  CPUs. If  an Intel non-SLe  CPU is  used, SMI#,
SMIACT#, and  FLUSH# are no  connects.  One design can  easily accomm-
odate both types of processors with minimal changes for upgrades.

***Configurations:...
***Features:...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89
***Info:

GENERAL DESCRIPTION

The  W860450/P is an  improved specification  version of  the W86C250A
Universal  Asynchronous  Receiver/Transmitter  [UART).   The  improved
specifications   ensure   compatibility   with  the   state-of-the-art
CPUs. Functionally, the W860450/P is equivalent to the INS8250A of the
National  Semiconductor. The W86C450/P  is fabricated  using WINBOND‘s
CMOS process.  The W860450/P performs serial-to-parallel conversion on
data  characters received  from a  peripheral device  or a  MODEM, and
parallel-to-serial  conversion on  data characters  received  from the
CPU. The CPU can read the complete status of the W860450/P at any time
during the functional  operation. Status information reported includes
the  type  and   condition  operation.   Status  information  reported
includes  the type  and  condition of  the  transfer operations  being
performed by the  W860450/P, as well as any  error conditions (parity,
overrun, framing, or break interrupt).

The  W860450/P includes  a programmable  baud rate  generator  that is
capable of dividing the timing  reference clock input by divisors of l
to  (2^16 -  4),  and producing  16x  clock for  driving the  internal
transmitter logic. Provisions are also  included to use this 16x clock
to  capability and  a  processor-interrupt system.  Interrupts can  be
programmed  to  the  user's  requirements,  minimizing  the  computing
required to handle the communications link.

***Versions:...
***Features:...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...