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**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section has been sourced from the
second.
Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93
***Notes::...
***Info:...
***Configurations:...
***Features:...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89
***Info:...
***Versions:...
***Features:
o Easily interfaces to most popular microprocessors.
o Adds or deletes standard asynchronous communication bit (start,
stop, and parity) to or from serial data stream.
o Holding and shift registers eliminate the need for precise
synchronization between the CPU and the serial data.
o Independently controlled transmit, receive, line status, and data
set interrupts.
o Programmable baud generator allow division of any input clock by 1
to (2^16 - 1) and generates the internal 16x clock.
o Independent receiver clock input.
o MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o Fully programmable serial-interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- l, 1.5 or 2-stop bit generation.
- Baud generation (DC to 56K baud).
o False start bit detection.
o Complete status reporting capabilities.
o TRl-STATE TTL drive capabilities for bidirectional data bus and
control bus.
o Line break generation and detection.
o Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation.
- Break, parity, overrun, framing error simulation.
o Fully prioritized interrupt system controls.
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
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