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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:...
***Configurations:...
***Features:
o   100% PC/AT compatible 
o   Fully supports the Intel Pentium microprocessor 
o   Three chip PC/AT solution: 82C596, 82C597 and 82C206 
o   Supports Intel Pentium CPU address pipelining 
o   IX clock source, supporting systems running up to 66 MHz 
o   Adaptive Write Back, direct-mapped cache with size 
    selections: 64K, 128K, 256K, 512K, 1Mb, 2Mb 
o   Programmable cache write policy: adaptive write back (AWB), 
    write-back or write through 
o   Fully programmable cache and DRAM read/write cycles 
o   Supports 3-2-2-2 cache burst read cycle at 66 MHz 
o   Built-in TAG auto-invalidation circuitry 
o   Support for two programmable non-cacheable/system memory "hole" 
    regions 
o   Supports two banks of 64-bit wide DRAMs with 256K, 
    512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs 
o   Supports DRAM configurations up to 128 Mb 
o   Supports 3-3-3-3 pipeline DRAM burst cycles 
o   DRAM post write buffer 
o   Provides Flash ROM support 
o   33 MHz asynchronous 32-bit VESA VL Local Bus support 
o   Performance oriented snoop-line comparator for VL/ISA bus masters 
o   Extended DMA page register 
o   Asynchronous CPU and VL bus interface 
o   AT bus clock speed programmability 
o   Low power, high speed CMOS technology 

**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89
***Info:...
***Versions:...
***Features:
o   Easily interfaces to most popular microprocessors.
o   Adds or deletes standard asynchronous communication bit (start, 
    stop, and parity) to or from serial data stream.
o   Holding and shift registers eliminate the need for precise 
    synchronization between the CPU and the serial data.
o   Independently controlled transmit, receive, line status, and data 
    set interrupts.
o   Programmable baud generator allow division of any input clock by 1 
    to (2^16 - 1) and generates the internal 16x clock.
o   Independent receiver clock input.
o   MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o   Fully programmable serial-interface characteristics:
    - 5, 6, 7, or 8-bit characters
    - Even, odd, or no-parity bit generation and detection
    - l, 1.5 or 2-stop bit generation.
    - Baud generation (DC to 56K baud). 
o   False start bit detection.
o   Complete status reporting capabilities.
o   TRl-STATE TTL drive capabilities for bidirectional data bus and 
    control bus.
o   Line break generation and detection.
o   Internal diagnostic capabilities:
    - Loopback controls for communications link fault isolation.
    - Break, parity, overrun, framing error simulation.
o   Fully prioritized interrupt system controls.


**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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