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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:...
***Configurations:...
***Features:
o   Single Chip 80386SX/286 PC/AT Compatible Solution for CPU Clock 
    Speeds to 20MHz
o   SX Mode or 286 Mode
o   Supports up to 8 MB DRAM using 1M or 256K Devices in by 1 or 4 
    configuration
o   Page Mode and 2 or 4-Way Interleaving
o   LIM EMS 4.0 Support in Hardware using 2 Sets of 32 EMS Registers
o   8-Bit or 16-Bit BIOS Support
o   Asynchronous AT Bus Clock
o   Supports up to 12 MHz Backplane Operation
o   Programmable DRAM Timing
o   Port 92 Alternate GATEA20 and Hot Reset
o   Shadow RAM support over entire C0000-DFFFF range in 16K 
    increments
o   BIOS Shadow support in 64K increments
o   Built-in Sleep Mode
o   Three-state control pins for board level testing
o   HCMOS Technology

**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89
***Info:

GENERAL DESCRIPTION

The  W860450/P is an  improved specification  version of  the W86C250A
Universal  Asynchronous  Receiver/Transmitter  [UART).   The  improved
specifications   ensure   compatibility   with  the   state-of-the-art
CPUs. Functionally, the W860450/P is equivalent to the INS8250A of the
National  Semiconductor. The W86C450/P  is fabricated  using WINBOND‘s
CMOS process.  The W860450/P performs serial-to-parallel conversion on
data  characters received  from a  peripheral device  or a  MODEM, and
parallel-to-serial  conversion on  data characters  received  from the
CPU. The CPU can read the complete status of the W860450/P at any time
during the functional  operation. Status information reported includes
the  type  and   condition  operation.   Status  information  reported
includes  the type  and  condition of  the  transfer operations  being
performed by the  W860450/P, as well as any  error conditions (parity,
overrun, framing, or break interrupt).

The  W860450/P includes  a programmable  baud rate  generator  that is
capable of dividing the timing  reference clock input by divisors of l
to  (2^16 -  4),  and producing  16x  clock for  driving the  internal
transmitter logic. Provisions are also  included to use this 16x clock
to  capability and  a  processor-interrupt system.  Interrupts can  be
programmed  to  the  user's  requirements,  minimizing  the  computing
required to handle the communications link.

***Versions:...
***Features:...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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