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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:
Date source: TimelineDateSort7_05.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Oct'93
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section has been sourced from the
second.
This chip was used on the Pentium 66MHz CPU complexes of Intel's
Xpress platform. Specifically the BXCPUPENT66 (Single 66MHz, eight
82491s) and BXCPU2XPENT (Dual 66 MHz, eight 82491s). Also found on P5
60/66MHz CPU complexes of IBM 9595/PC Server 300/500 systems.
***Info:...
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***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
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**HT12/+/A Single 286 AT Chip with EMS support c:Aug90
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**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
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**HT44 Secondary Cache c:Jun92...
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**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89
***Info:
GENERAL DESCRIPTION
The W860450/P is an improved specification version of the W86C250A
Universal Asynchronous Receiver/Transmitter [UART). The improved
specifications ensure compatibility with the state-of-the-art
CPUs. Functionally, the W860450/P is equivalent to the INS8250A of the
National Semiconductor. The W86C450/P is fabricated using WINBONDâs
CMOS process. The W860450/P performs serial-to-parallel conversion on
data characters received from a peripheral device or a MODEM, and
parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the complete status of the W860450/P at any time
during the functional operation. Status information reported includes
the type and condition operation. Status information reported
includes the type and condition of the transfer operations being
performed by the W860450/P, as well as any error conditions (parity,
overrun, framing, or break interrupt).
The W860450/P includes a programmable baud rate generator that is
capable of dividing the timing reference clock input by divisors of l
to (2^16 - 4), and producing 16x clock for driving the internal
transmitter logic. Provisions are also included to use this 16x clock
to capability and a processor-interrupt system. Interrupts can be
programmed to the user's requirements, minimizing the computing
required to handle the communications link.
***Versions:...
***Features:...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
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