[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:
o   Highly Integrated, Single Chip 80386SX AT Compatible Solution
o   Special Multiple Context Hardware EMS Support (LIM 4.0 compatible) 
    using 2 sets of 32 EMS Registers
o   Single or Dual BIOS
o   Shadow RAM support over entire C0000 to DFFFF Address range in 16K 
    increments, E0000 to FFFFF in 64K increments
o   Page Mode and 2-way Interleaving
o   Supports up to 12MHz AT Bus Clock
o   High Performance Muxed DRAM Interleave
o   Programmable DRAM timing
o   Asynchronous AT Bus Clock
o   Three-State Test Mode
o   16-Bit ROM BIOS Support

HT 18A/B Special Features
o   16 and 20 MHz CPU Clock Speeds
o   Supports up to 8M CPU Memory using combinations of 64K, 256K and 
    1M Devices
o   4 Bank, 4-way Interleave Mode

HT18C/25MHz Special Features
o   16, 20 and 25MHz CPU Clock Speeds
o   Supports up to 20M with EMS CPU Memory using combinations of 256K, 
    1M and 4M Devices

**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83769          Local Bus IDE Solution                           <94
***Info:
GENERAL DESCRIPTION

The W83769  is a  high-performance, low-cost, highly  integrated logic
design  for IDE hard  disk applications  in PCI  (Peripheral Component
Interconnect)  local  bus systems.  It  provides  a  bridge between  a
standard  IDE  drive  and the  PCI  local  bus.  The W83769  is  fully
compatible  with the  ANSI ATA  3.0 specifications  for IDE  hard disk
operation  and the  PCI SIG  revision 2.0  specifications for  the PCI
local bus  protocol. Packaged in  a 100-pin PQFP, the  W83769 directly
supports the 32-bit PCI bus without requiring any external TTLs.

The W83769  operates at up to 50  MHz and provides a  full 32-bit data
path to the PCI bus. Doubleword read and write operations are provided
via  internal   control  and  conversion  logic.   Write  posting  and
read-ahead  allows CPU  memory  cycles to  run  concurrently with  IDE
cycles and improves the hard disk buffer-to-host transfer rate.

The IDE  drive interface timing  of the W83769 is  completely software
programmable,  including command  active/recovery  timing and  address
setup-hold   timing  for   each  drive.   The  device   supports  Fast
ATA/Enhanced  IDE  mode  3  timing  and IORDY  monitoring  for  better
performance.   The  W83769  directly  supports four  IDE  drives  with
170/1F0   dual   IDE  connectors.   The  IO base   addresses  of   the
primary/secondary  IDE connector  are exchangeable  by  power-on strap
option.

***Versions:...
***Features:...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...