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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9090  Universal PC/AT Clock Chip                            <oct88
***Info:...
***Versions:...
***Features:
o   Generates all essential Clock Signals for P.C.'s.
o   Supports 8086/ 8088/ 80286/ 80386SX/ 80386-based designs.
o   Clock Options of 60, 50, 48, 40, or 32 MHz and others.
o   Requires only one Crystal and few RC components.
o   Two Independent Clock Generators.
o   Glitch free switching for both Clock Generators.
o   All outputs capable of 8 mA Drive.
o   Advanced Bipolar technology.
o   40 Pin Plastic Dip, or 44 Pin PLCC.

**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
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*Unresearched:...
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*Winbond...
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96
***Notes:...
***Info:...
***Versions:...
***Features:
o  Pin-to-pin backward compatible with W83759 VL-IDE Interface chip
o  VESA VL-Bus Rev 2.0 compatible, connects directly to local bus and 
   four IDE drives
o  Direct interface to various ANSI ATA/ATA-2/FAST ATA/IDE-2/Enhanced 
   IDE drives
o  Supports 32 and 16-bit data transfer
o  Fully software programmable for command active/recovery time and 
   address setup, data hold time
o  Built-in VL-Bus to 16-bit IO data buffer for special applications
o  Fully supports Enhanced IDE features, including Fast PIO, Mode 3/4, 
   IORDY flow control, prefetch control
o  Supports dual channels to allow up to four drives or non-disk 
   devices (ATAPI CD-ROM and tape drives)
o  Pipeline pre-fetched reads and posted writes for concurrent disk 
   and host operations
o  Independent access timing for all drives (primary/secondary and 
   master/slave)
o  All Enhanced IDE new features may be disabled/enabled via driver 
   or power-on setting by per drive selectability
o  ATA/Mode 0-4 PIO speed may be set as default timing of each drive 
   via power-on jumper setting
o  Supports slave DMA mode protocol (reserved)
o  Supports auto power-down, standby, suspend APM power management 
   state for green PCs
o  Primary and secondary channel can be independently enabled/disabled 
   by software or jumper setting
o  Supports drivers for DOS, Windows, OS/2, UNIX, and Netware
o  Packaged in 100-pin QFP

**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
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