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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct Mapped Cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - One programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer and interrupt controllers
    - Optional PS/2 style IRQ1 and 12 latching
o   VESA VL interface:
    - Conforms to the VESA v2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83757          SUPER I/O  CHIP                                  <92
***Info:
GENERAL  DESCRIPTION 

The W83757 is a super multi  I/O chip that combines the functions of a
Floppy Disk Drive adapter, serial (UART)/parallel adapter, IDE bus and
game  port.   The W83757's  disk  drive  adapter  functions include  a
standard   Floppy  Disk  Drive   controller,  data   separator,  write
precompensation  circuit,  decode logic,  data  rate selection,  clock
generator,  drive interface  control logic,  interrupt and  DMA logic,
thus greatly  reducing the number of components  required to interface
floppy disk  drives. As a UART,  the chip supports  serial to parallel
conversion on data  characters received from a peripheral  device or a
MODEM, and  parallel to serial conversion on  data characters received
from the CPU. The CPU can read  the complete status of the UART at any
time  during operation.  The UART  includes a  programmable  baud rate
generator, complete MODEM control capability and a processor-interrupt
system.  As a parallel port, the W83757 provides the user with a fully
bidirectional parallel centronics-type  printer interface. Besides the
above functions, this chip also supports two Embedded Hard Disk Drives
(AT bus interface) and a game port decoder.
***Versions:...
***Features:...
**W83767F         ??           Multi I/O  [no datasheet]
**W83777F/87F     Power I/O   (Multi I/O)                          <95...
**W83877F         WINBOND I/O (Multi I/O)                          <96...
**W83877TF/TG/TD  WINBOND I/O (Multi I/O)                          c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O)                          c97...
**W83977TF        WINBOND I/O (Multi I/O)                          c97...
**W83977EF        WINBOND I/O (Multi I/O)                          <98...
**W83977ATF       WINBOND I/O (Multi I/O)                          <98...
**
**Disk Controller:
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96...
**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...