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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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HT209D   VGA
HT216-32 Local Bus VGA Controller

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**W83757          SUPER I/O  CHIP                                  <92
***Info:...
***Versions:...
***Features:
o   Compatible with IBM PC AT/XT Disk Drive systems.
o   Supports up to two 3.5", or 5.25“ 360K/720K/ 1.2M or 1.44M Floppy 
    Disk Drives.
o   Emulates NEC765A in IBM environment.
o   Supports variable write precompensation with track selectable 
    capability.
o   Built-in address mark detection circuit to simplify the read 
    electronics.
o   IBM PC system address decoder.
o   Supports up to two Embedded Hard Disk Drives (IDE AT bus).
o   Single 24 MHz crystal input.
o   Fully programmable serial-interface characteristics:
    - 5, 6, 7 or 8-bit characters.
    - even, odd or no parity bit generation and detection
    - 1, 1.5 or 2 stop bit generation.
o   Internal diagnostic capabilities:
    - loopback control for communications link fault isolation
    - break, parity, overrun, framing error simulation.
o   Programmable baud rate generator allows division of any input 
    clock 
    by 1 to (2^16-1) and generates the internal 16 X clock.
o   Compatible with IBM printer port.
o   2u high performance CMOS technology.
o   100-pin QFP.

**W83767F         ??           Multi I/O  [no datasheet]
**W83777F/87F     Power I/O   (Multi I/O)                          <95...
**W83877F         WINBOND I/O (Multi I/O)                          <96...
**W83877TF/TG/TD  WINBOND I/O (Multi I/O)                          c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O)                          c97...
**W83977TF        WINBOND I/O (Multi I/O)                          c97...
**W83977EF        WINBOND I/O (Multi I/O)                          <98...
**W83977ATF       WINBOND I/O (Multi I/O)                          <98...
**
**Disk Controller:
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96...
**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89...
**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...