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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547 Python PTM3V c:94
***Notes:...
***Info:...
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the 3.3V/5.0V Pentium processors
o Three chip solution:
- 82C547 System Controller (SYSC) (160-pin PQFP)
- 82C546 AT Bus Controller (ATC) (208-pin PQFP)
- 82C206 Integrated Peripheral Controller (IPC) (84-pin PLLC
or 100-pin PQFP)
o Two buffer/translator support chips:
- 82C606A (100-pin PQFP)
- 82C606B (100-pin PQFP)
o Supports Pentium CPU address pipelining
o 1X clock source, supporting systems running Pentium processor
bus clocks up to 60MHz
o Write-back, direct-mapped cache with size selections:
64KB, 128KB, 256KB, 512KB, 1MB and 2MB
o Programmable cache write policy: write-back or write-through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycles at 60MHz
o Built-in tag auto-invalidation circuitry
o Support for two programmable non-cacheable memory regions
o Options for cacheable, write-protected, system and video BIOS
o Supports two banks of 64-bit wide DRAMs with 256KB, 512KB, 1MB
2MB, 4MB and 8MBx36 Page Mode
o Supports DRAM configurations up to 128MB
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Support for flash ROM
o Shadow RAM option
o Hidden refresh with CAS-before-RAS refresh supported
o High-performance 32-bit local bus support
o Performance-oriented snoop-line comparator for VL/ISA
bus masters
o External DMA page register
o Turbo/slow speed selection
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Transparent 8042 emulation for Fast CPU Reset and GATEA20
generation
o Supports Ports 92h, Gate A20, and Fast Reset
o Mixed voltage (3.3V and 5.0V), low-power, high speed, 0.8
micron CMOS technology
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W83C553F System I/O Controller With PCI Arbiter c:sep95
***Info:...
***Versions:...
***Features:
High Integration PCI-ISA solution
o Optimized for lowest system cost
o Complies with PCI Revision 2.0 specification
o Universal PCI device supporting x86 and PowerPC (non-x86) modes of
operation
Nand tree on most signal pins to facilitate board level testing in PCB
manufacturing environment
Integrated PCI Bus Master IDE controller
o Dual channel Bus Master IDE for up to 4 peripherals, including hard
drives, ATAPI (IDE) CD-ROMs, tapes, etc.
o Multi-threading capability allows two simultaneous I/O processes
o Independent IDE Timing registers allow fast/slow devices on the
same cable
o Two independent DMA channels for Bus Master scatter/gather DMA
transfers across the PCI bus
o Large 64 byte DMA FIFO for zero wait state PCI burst transfers
o Support for multiword DMA Mode 1 (13.3 MB/s), Mode 2 (16.6 MB/s)
IDE drives
o PIO IDE support for Modes 0-4 disks
o Edge rate controlled outputs directly drive IDE headers
o Four byte pre-fetch and posted write buffers
o DMA channels can be re-configured for P-n-P motherboard devices
o Software and register set compatible with Intel Bus Master PCI-IDE
specification (SFF 8038i)
o Supported by existing device drivers for MS-DOS, Windows, NT 3.1,
NT 3.5x, NT4.0, OS/2 2.1, OS/2 Warp, NetWare 3.12 and 4.x**
o Recompiled PowerPC device drivers also available
>** OS/2, Novell driver by DTC
PCI Arbiter
o Supports CPU, IDE, ISA and five additional bus masters
o Programmable access windows allow fine tuning of PCI access for
each bus master
o Can be disabled on power-up via strapped pin
Power Management Break Event support for Green PC applications
Built-in Integrated Peripheral Controller (IPC) with standard PC-AT
peripherals
o Two 82C37A DMA controllers (types A, B, and F)
- 32-bit addressing allows use of alternate CPUs, such as PowerPC
- supports multiple 8-bit and 16-bit scatter/gather DMA channels
o Two 82C59A interrupt controllers
- all IRQ inputs may be programmed for edge or level sensitivity
o One 82C54 counter/timer
o Routes external PCI interrupts to a software-selectable interrupt
channel
PCI Bus Interface
o PCI Revision 2.1 compliant
o PCI clock frequencies up to 33 MHz at 5V
o Supports delayed completion for ISA cycles
o Active address decoding for internal I/O devices
o Subtractive decoding for ISA bridge, KBC and RTC
o Supports disconnection (with retry) for slow internal accesses to
improve latency
o Short PCI bus ownership when mastering to minimize overall system
latency
o Fast DMA transfers from I/O devices to PCI agents as a master
o Separate request and grant signals for ISA DMA and IDE controllers
ISA Bus Bridge
o Full implementation of a standard ISA bus
o Separate ISA and IDE data buses reduce noise and increase system
performance
o Synchronous PCI-to-ISA interface with direct drive for 5 ISA slots
XD-Bus interface
o Support for BIOS ROM or PowerPC systems boot ROM
o Support for flash EPROM
o Provides keyboard controller connections
o Provides real-time clock connections
o Provides data buffer control
Miscellaneous
o Port B support
o Port 92 support
Uses 0.6um, ultra-low power CMOS technology for Rev. E and below;
0.5um for Rev. G. Packaged in a 208-pin PQFP package
**W83628F/29D PCI TO ISA Bridge Set c98...
**W83626F/D LPC TO ISA Bridge Set <00...
**
**Multi I/O:
**W83757 SUPER I/O CHIP <92...
**W83767F ?? Multi I/O [no datasheet]
**W83777F/87F Power I/O (Multi I/O) <95...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
*General Sources:...
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