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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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*Unresearched:...
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*Western Digital...
*Winbond...
**W83C553F System I/O Controller With PCI Arbiter c:sep95
***Info:
The W83C553F Enhanced System I/O (SIO) Controller with PCI Arbiter is
a highly integrated device intended for use in any Peripheral
Component Interconnect (PCI) system, supporting x86 or PowerPC
(non-x86) type microprocessors. It supports all PCI 2.1 compliant CPU
bridge implementations and directly interfaces with PCI and ISA
industry standard buses, including two direct drive IDE channels
supporting up to four peripherals.
The W83C553F is a universal PCI device which can be used with many
CPU-to-PCI bridge solution. The W83C553F includes 32-bit ISA DMA
addressing (rather than 24-bit) to simplify its use in systems using
re-compiled versions of 32-bit operating systems (such as Windows NT
running on PowerPC, Alpha, or other RISC CPU).
The peripheral controller integrated into the W83C553F includes two
enhanced seven channel 82C37A 32-bit DMA controllers that support fast
DMA transfers with a four byte line buffer to isolate the PCI bus from
the ISA bus, enhancing performance. Both DMA controllers support
scatter/gather data transfer capability.
The W83C553F Enhanced SIO controller provides the bridge between the
PCI bus and the ISA expansion bus. It also integrates a PCI bus master
IDE controller, an eight master PCI arbiter (which may be disabled if
desired) and many of the common I/O functions found in today's ISA
based PC systems. The W83C553F incorporates the logic for a complete
PCI interface (master and slave) and ISA interface (master and
slave). Also included is PCI and ISA arbitration, 14 level interrupt
controller, a 16-bit BIOS timer, three programmable counter/timers,
non-maskable-interrupt (NMI) control logic and register support for
power management break events.
The built-in Enhanced PCI IDE Controller is a highly integrated dual
port controller, providing a high performance data path between IDE
devices and the PCI bus. Four IDE chip select signals provide
accessing of up to four devices. Each device has its own programmable
registers for selecting 16-bit and 32-bit data pipelined transfer
rates, read-ahead and posted writes. A large 64 Byte DMA FIFO buffers
data to and from the IDE disks enabling the integrated scatter/gather
DMA controller to efficiently perform zero wait state burst transfers
across the PCI bus when enough data is available in the FIFO. Bus
master IDE significantly improves the overall system performance of a
multi-master PCI configuration by greatly reducing the bus and CPU
utilization required for the disk and CD-ROM interface. Burst data
transfers at 33 MHz can be sustained at 132 MB/s on the PCI bus.
The integrated bus-mastering PCI-IDE core is the original Sonata
W83789F core with some modification of interrupt routing. This
controller is fully compliant to Intel's Bus-Mastering Controller and
SFF8038i specifications. BIOS support has been incorporated in all the
leading BIOS companies' software. Driver software, previously tested
and qualified for the W83789F, is available from Winbond Systems
Laboratory for all major operating systems, including recompiled
PowerPC versions.
***Versions:...
***Features:...
**W83628F/29D PCI TO ISA Bridge Set c98...
**W83626F/D LPC TO ISA Bridge Set <00...
**
**Multi I/O:
**W83757 SUPER I/O CHIP <92...
**W83767F ?? Multi I/O [no datasheet]
**W83777F/87F Power I/O (Multi I/O) <95...
**W83877F WINBOND I/O (Multi I/O) <96...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
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