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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
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*OPTi...
**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
    - Auto clock detection
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow, and CAS-before-RAS refresh
    - Eight RAS lines to support eight banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
    - Strong drive on MA lines (12/24mA)
    - Supports asymmetric DRAMs
o   Power management:
    - Support for SMM (System Management Mode) for system power
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software, and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - Programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer, and interrupt controllers
    - Optional PS/2 style IRQ1 and IRQ12 latching
o   VESA VL interface:
    - Conforms to the VESA V2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, and write protection for video, 
      adapter, and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU Reset and Gate A20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD7625     Desktop Buffer Manager                          <10/01/92
***Info:...
***Versions:...
***Features:
ADDRESS BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD8110, WD7710, and WD7910 based designs 
    with WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connect to AT Address Bus SA1:19 and LA17:23 with 24 mA 
    drive
o   Power Management Control (PMC) input MUX 
o   General purpose suspend/resume and power supply control logic
o   Fifteen-bit Power Management Control (PMC) output register and 
    control logic
o   Low power request and resume signal delay simplify the design of 
    the power supply
o   Watchdog timer for system idle detection
o   DRAM WE signal from WD7xc10 inversion and buffering
o   RESIN output generation from reset switch (RSTSW)
o   System Reset generation
o   Chip select decoding for registers in the WD7625LV Data Buffer 
    Function
o   144-pin SQFP package

DATA BUFFER FEATURES
o   Allows WD7SC10A, WD7855, WD7710, and WD7910 based designs with 
    WD7620/30 for laptop or notebook systems
o   Will work in three different power supply modes:
    - 3.3V only
    - 5V only
    - Mix mode 3.3V and 5V
o   Direct connection to AT data bus; 20K integrated pull-up for 
    SD(0:7)
o   Direct connection to IDE data bus
o   Two general purpose 8-bit I/O registers:
    - Register A
    - Register B
o   One general purpose 8-bit I/O Register C, with single bit 
    set/reset control
o   One general purpose 1-bit I/O Register Y0
o   One 4-bit general purpose input only Register Z
o   DRQ multiplexing plus 20K integrated pull-down
o   DACK demultiplexing
o   SMEMR, SMEMW signals plus 22K internal pull-up
o   144-pin SOFP package

**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
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