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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance  PC/AT platforms.   This chipset will  support 486SX/
DX/DX2/DX4  and P24T microprocessors  in the  most cost  effective and
power  efficient  designs  available  today.  For  power  users,  this
chipset offers optimum performance for systems running up to 50MHz.

Based  fundamentally  on  OPTi's   proven  82C801  and  82C802  design
architectures,  the 82C895 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The  820895  supports the  latest  write-back  processor designs  from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for   compatibility  and   performance.   It  also   includes  an
82C206-compatible  Integrated Peripherals Controller  (IPC). all  in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.

2.1 Power Management

This block diagram [see  datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN  strategy.  System designs  can easily accommodate
both SLe  and non-SLe  CPUs. If  an Intel non-SLe  CPU is  used, SMI#,
SMIACT#, and  FLUSH# are no  connects.  One design can  easily accomm-
odate both types of processors with minimal changes for upgrades.

***Configurations:...
***Features:...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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*Western Digital...
**WD7625     Desktop Buffer Manager                          <10/01/92
***Info:
INTRODUCTION
This document describes the two separate functions, Address Buffer and
Data Buffer,  available in  the WD7625LV chip.  A strapping  input pin
selects  the Data  Buffer  Function when  strapped  low, otherwise  it
selects the Address Buffer Function.

GENERAL DESCRIPTION
The  WD7625LV is  a  combination design  which  includes two  separate
functions: Address  Buffer and Data  Buffer in one chip.   A strapping
input pin  selects the  Data Buffer  Function if  it is  strapped low;
otherwise, it  selects the Address  Buffer Function. For  designs that
use  both  the data  buffer  and  the  address buffer  functions,  two
WD7625LV devices are needed in the system.

In the Address Buffer Function,  the WD7625LV is an address buffer and
power management chip.  

In the Data Buffer Function, the WD7625LV is a data buffer, IDE buffer
and I/O register device for the WD7x00 16-bit chip sets.
***Versions:...
***Features:...
**WD8120LV   Super I/O [no datasheet]                                ?
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