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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:
o   16 or 20 MHz Options.
o   Enhanced fast page mode design.
o   Programmable wait state options.
o   Shadow Ram feature.
o   Supports 8 M byte of on board memory.
o   Can use 256K x 1, 1 Meg x 1, and 256K x 4 DRAMs or a mix.
o   Supports 100 ns DRAMs at 16 MHz and 80 ns at 20 MHz.
o   Automatic remapping of 640K - 1 M RAM to top of the address space.
o   Advance CMOS Technology.
o   100 pin Flatpack.

**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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**WD7625     Desktop Buffer Manager                          <10/01/92
***Info:
INTRODUCTION
This document describes the two separate functions, Address Buffer and
Data Buffer,  available in  the WD7625LV chip.  A strapping  input pin
selects  the Data  Buffer  Function when  strapped  low, otherwise  it
selects the Address Buffer Function.

GENERAL DESCRIPTION
The  WD7625LV is  a  combination design  which  includes two  separate
functions: Address  Buffer and Data  Buffer in one chip.   A strapping
input pin  selects the  Data Buffer  Function if  it is  strapped low;
otherwise, it  selects the Address  Buffer Function. For  designs that
use  both  the data  buffer  and  the  address buffer  functions,  two
WD7625LV devices are needed in the system.

In the Address Buffer Function,  the WD7625LV is an address buffer and
power management chip.  

In the Data Buffer Function, the WD7625LV is a data buffer, IDE buffer
and I/O register device for the WD7x00 16-bit chip sets.
***Versions:...
***Features:...
**WD8120LV   Super I/O [no datasheet]                                ?
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