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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:
Green version of the 82C802. Supports cached 486 systems running from
20 MHz to 50 MHz. Also supports write-back cache and VESA LB. PCI is
also supported via the 82C822 bridge chip.
This is an amalgamation of two different datasheets, the 802G and
802GP. There is very little difference, see the features section.
***Info:...
***Configurations:...
***Features:...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
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**WD7615 Desktop Buffer Manager <04/15/92
***Info:...
***Versions:...
***Features:
o Allows the WD7XC10 based designs to work with a generic "Super l/O"
device or with the WD76C20 and WD76C30
o Replaces majority of external "glue" logic, up to 13 devices:
- AT bus address buffers with 24 mA drive
- AT bus interrupt multiplexing, and interrupt pull ups.
- AT bus DRQ multiplexing and internal pull downs.
- Keyboard/mouse interrupt latching and clearing functions
- A20 Gate logic
- Controlling the IDE data bit 7 at address 3F7H.
o Allows implementation of a desktop system with only three external
devices
o Direct connect to AT address bus SA1 through SA19 and LA17 through
LA23 with 24 mA drive
o DAC multiplexing and RESET generation
o DRAM WE signal from WD76C10 inversion and buffering
o SMEMR and SMEMW generation with 24mA direct drive
o Divide by 2 or divide by 4 clock output
o 136-pin MQFP package
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
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