[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:
The  82C802G/GP  provides  a  highly  integrated  solution  for  fully
compatible,  high  performance  PC/AT  platforms.  This  chipset  will
support  486SX/DX/DX2/DX4 and  P24T microprocessors  in the  most cost
effective  and power  efficient  designs available  today.  For  power
users this  chipset offers optimum performance for  systems running up
to 50MHz.

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C802G/GP  adds additional  memory configurations
and  extensive power management  control for  the processor  and other
motherboard components.

The  82C802G/GP supports  the latest  in write-back  processor designs
from Intel, AMD, and Cyrix, as  well as supporting the AT bus and VESA
local  bus for  compatibility and  performance.  It  also  includes an
82C206  Integrated  Peripherals  Controller  (IPC), all  in  a  single
208-pin PQFP (Plastic Quad Plat Pack) package for low cost.

Power Management Block
Figure  2-1  [see  datasheet]   exemplifies  the  flexibility  of  the
82C802G/GP/82C602   GREEN   strategy.   System  designs   can   easily
accommodate  both SLe and  non-SLe CPUs.  If an  Intel non-SLe  CPU is
used. SMI#, SMIACT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:
GENERAL
The WD76C30/LV device provides three  functional groups.  It is a Per-
ipheral Controller, Interrupt Multiplexer, and Clock Generator.

The  low power  CMOS  WD76C30/LV  is a  single  device solution  which
provides  interrupt multiplexing logic,  clock generation,  two serial
ports, and one bidirectional parallel port.

Interrupt  multiplexing logic interfaces  the PC/AT  interrupt request
lines with the WD76C10 Single Chip AT Controller.

Integrated clock generation circuitry uses  the 48 MHz input signal to
generate the 1.8462, 3.072, and 8.0 MHz clocks used internally for the
two serial  ports, a 9.6 MHz  Signal used for  the keyboard controller
and  floppy controller,  a programmable  duty/frequency clock  for the
80287 coprocessor, and  a 16 MHz clock for  driving the WD76C10 Single
Chip AT Controller, and floppy controller.

For low power implementations  such as laptops, oscillator disable and
sleep modes are available to power down unused logic.

The bidirectional  parallel port is software configurable  as either a
PC/AT or a PS/2 compatible port. The parallel port data lines and open
drain printer signals have high current drive capabilities.

Each ACE is  programmable as either a WD16C550  or WD16C450 compatible
device. Each WD16C550 configured ACE  is capable of buffering up to 16
bytes  of  data  upon   reception,  relieving  the  CPU  of  interrupt
overhead.  Buffering  of data  also  allows  greater  latency time  in
interrupt servicing which is vital in a multitasking environment. Each
ACE has a maximum recommended data rate of 512 Kbaud.

WD76C30/LV DIFFERENCES
Both the  WD76C30 and WD76C30LV  operate with two power  supplies. The
WD76C30 logic  is powered  by a 5.0  volt supply, while  the WD76C30LV
logic is powered  by a 3.3 volt supply.  The  parallel and serial port
interfaces are only supported by the WD76C30.

PERIPHERAL CONTROLLER
The peripheral controller is  functionally equivalent to the WD16C452/
552. The  mode of operation of  the serial ports and  parallel port is
selectable  via  the  Mode  Select  Register.   Each  serial  port  is
configurable as either a FIFO  enhanced ACE (WD16C550 compatible) or a
standard ACE (WD16C450). The parallel port is configurable as either a
PS/2 bidirectional parallel port  or a PC/AT compatible parallel port.
A detailed description of the  Mode Selection Register is described in
the parallel port section.

***Versions:...
***Features:...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...