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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:...
***Configurations:...
***Features:...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:...
***Versions:...
***Features:
o   Two fully programmable and independent serial I/O ports 
    configurable as PC/AT compatible (WD16C452) or PS/2 
    compatible (WD16C552)
    - Loopback controls for communications link fault isolation for 
      each ACE
    - Line break generation and detection for each ACE
    - Complete status reporting capabilities
    - Generation and stripping of serial asynchronous data control 
      bits (start, stop, parity)
    - Programmable baud rate generator and MODEM control signals for 
      each port
    - Programmable baud rate generator input clock
    - Optional 16 byte FIFO buffers on both transmit and receive of 
      each port for CPU relief during high speed data transfer
    - Programmable FIFO threshold levels of 1 , 4, 8, or 14 bytes on 
      each port
o   Parallel port configurable as a fully Centronics or PS/2 
    compatible, bidirectional parallel port
o   Independently programmable parallel port
o   Interrupt multiplexing logic
    - Selectable multiplexing logic for connecting PC/AT interrupt 
      request lines to the WD76C10 single chip AT controller
o   Clock generation circuitry
    - 80287 coprocessor clock generation
    - WD76C10 and floppy controller clock generation
    - 8042 keyboard clock generation
o   Built-in testability features
o   Hardware or software controllable sleep mode
o   CMOS implementation for high speed and low power requirements 
o   Pulse extension on IRQ inputs
o   84-pin PLCC and PQFP packages

**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
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