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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**450NX (?) 06/29/98:...
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**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88
***Info:...
***Configurations:
GC101 CPU and Peripheral Controller
GC102 as Address Buffer
GC102 as Data Buffer
chips suffixed -12 are 12 MHz, -16 are 16 MHz.
Versions:
HT101, HT102, renamed parts.
HT101A no idea of difference
***Features:...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89...
**GCK113 80386 AT Compatible Chip Set c:oct89...
**GCK181 Universal PS/2 Chip Set c:Mar89...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
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*Western Digital...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:
GENERAL
The WD76C30/LV device provides three functional groups. It is a Per-
ipheral Controller, Interrupt Multiplexer, and Clock Generator.
The low power CMOS WD76C30/LV is a single device solution which
provides interrupt multiplexing logic, clock generation, two serial
ports, and one bidirectional parallel port.
Interrupt multiplexing logic interfaces the PC/AT interrupt request
lines with the WD76C10 Single Chip AT Controller.
Integrated clock generation circuitry uses the 48 MHz input signal to
generate the 1.8462, 3.072, and 8.0 MHz clocks used internally for the
two serial ports, a 9.6 MHz Signal used for the keyboard controller
and floppy controller, a programmable duty/frequency clock for the
80287 coprocessor, and a 16 MHz clock for driving the WD76C10 Single
Chip AT Controller, and floppy controller.
For low power implementations such as laptops, oscillator disable and
sleep modes are available to power down unused logic.
The bidirectional parallel port is software configurable as either a
PC/AT or a PS/2 compatible port. The parallel port data lines and open
drain printer signals have high current drive capabilities.
Each ACE is programmable as either a WD16C550 or WD16C450 compatible
device. Each WD16C550 configured ACE is capable of buffering up to 16
bytes of data upon reception, relieving the CPU of interrupt
overhead. Buffering of data also allows greater latency time in
interrupt servicing which is vital in a multitasking environment. Each
ACE has a maximum recommended data rate of 512 Kbaud.
WD76C30/LV DIFFERENCES
Both the WD76C30 and WD76C30LV operate with two power supplies. The
WD76C30 logic is powered by a 5.0 volt supply, while the WD76C30LV
logic is powered by a 3.3 volt supply. The parallel and serial port
interfaces are only supported by the WD76C30.
PERIPHERAL CONTROLLER
The peripheral controller is functionally equivalent to the WD16C452/
552. The mode of operation of the serial ports and parallel port is
selectable via the Mode Select Register. Each serial port is
configurable as either a FIFO enhanced ACE (WD16C550 compatible) or a
standard ACE (WD16C450). The parallel port is configurable as either a
PS/2 bidirectional parallel port or a PC/AT compatible parallel port.
A detailed description of the Mode Selection Register is described in
the parallel port section.
***Versions:...
***Features:...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
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