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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:...
***Versions:...
***Features:
o 84-pin PLCC and PQFP packages
o 5V supply requirement (WD76C20)
3.3V supply requirement (WD76C20LV)
o 3.0V battery backup supply for the RTC and 114 byte SRAM (WD76C20)
2.4V battery backup supply for the RTC and 114 byte SRAM
(WD76C20LV)
o Implemented in a low-power, high-performance, 1.25 micron CMOS
technology process
o Floppy Disk Controller (FDC) software transparent power-down mode
with low standby ICC current. FOC features:
- 256 tracks support
- 100% software compatible with NEC 765A
- Integrated high-performance DPLL data separator:
- 125, 250, 300, 500 Kb/sec and 1 Mb/sec data rates
- Option to select 150 Kb/sec FM and 300 Kb/sec MFM data
rates only
- Automatic Write Precompensation:
- Defeat option
- Inner track value of 125 or 187 ns pin selectable
- On chip clock generation:
- 2 TTL clock inputs, or
- Single 16 or 32 MHz crystal circuit and one TTL clock input
- Power Qualified Reset
- Enable PQR in W076C20
- Disable PQR in W076C20LV
- Host interface read/write accesses compatible with 80286
microprocessors at speeds up to 12 MHz with 0 wait states
- Direct floppy disk drive interface - no buffers needed
- 48 mA sink output drivers
- Schmitt Trigger input line receivers
- FDC direct PC XT/AT interface compatibility
- Floppy Control and Operations Registers on chip
- In PC/AT mode, provides required signal qualification to DMA
channel
- IBM BIOS compatible
- Dual-speed spindle drive support
- PS/2 type drive support
o Real Time Clock (RTC) features:
- Software compatible with Motorola MC146818A.
- Internal time base and oscillator circuitry
- Counts seconds, minutes, and hours
- Counts days of the week, date, month, and year
- Time base input for 32.768 KHz square wave
- Time base oscillator for parallel resonant crystals
- Binary or BCD representation of time, calendar, and alarm
- 12- or 24-hour clock with AM and PM in 12-hour mode
- Daylight savings time option
- Automatic leap year compensation
- Interfaced with software as 128 RAM locations
- 114 bytes at general purpose RAM
- Status bit indicates data integrity
- Bus compatible interrupt signals (IRQ)
- Three interrupts are separately software maskable and testable:
- Time-at-day alarm - once-per-second to once-per-day
- Periodic interrupt rates tram 122 us to 500 ms
- End-at-clock update cycle
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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