[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486SX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct mapped cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
[- Supports external single-chip cache modules from thyroid-party ]
[ vendors for high performance at 50MHz ]
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow. and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
[- Eight RAS lines to support four banks of DRAM ]
- Programmable wait states for DRAM reads and writes
[- Programmable memory holes for supporting ISA memory ]
- Enhanced DRAM configuration map
[- Strong drivers on the MA lines (12/24mA) ]
[- Supports asymmetric DRAMs ]
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
[- CPU clock control ]
- Programmable wake-up events through hardware, software, and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
[- Programmable GREEN event timer ](802G only)
[- Individually programmable peripheral ](802GP only)
o ISA interface:
- 100% IBM PC/AT ISA compatible
[- Programmable edge- or level-trigger interrupts ]
- integrates DMA, timer and interrupt controllers
[- Slew rate control for output drivers ]
- Optional PS/2 style IRQ1 and IRQ12 latching
o VESA VL interface:
- Conforms to the VESA V2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features: (802G only)
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter, and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o [Miscellaneous features: ](802GP only)
[- Full support for flash, write protection, L1/L2 ]
[ cacheability for video, adapter, and system BIOS ]
[- Provides Micro Channel bridge support ]
[- 10-/16-nit I/O decodes ]
[- Enhanced arbitration scheme ]
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high~speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:
GENERAL DESCRIPTION
The WD76C20 is a member of the WD7600 chip set which provides a
cost-effective, power-efficient solution to PC systems design,
especially those relating to "lap-top" devices. The set includes the
WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together
these chips provide all necessary logic to build a fully integrated
system board for several varieties of IBM PC/AT compatibles including
systems using 80286, 80386SX, and 80C286 processors.
As part of this chip set, the WD76C20 provides these integral
functions:
o Bus Interface Logic
o IDE Interface
o Chip Select Logic
o Floppy Disk Controller
o Real Time Clock
o Suspend/Resume Logic
The Floppy Disk Controller (FDC) component provides necessary timing
and signalling between the host processor peripheral bus and a floppy
disk drive through a cable connector.
The Real Time Clock component provides calendar and clock information
for the system.
The IDE Interface controls buffering between the system's AT Bus and
PC/AT compatible IDE drive interface.
The Bus Interface Logic controls buffering of data between the
system's AT Bus and the WD76C20.
The Chip Select Logic section provides decoding for selected chip
functions both within the WD76C20 and on the PC/AT motherboard.
Suspend/Resume Logic provides support for chip set power-down and
resume sequences.
***Versions:...
***Features:...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved