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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*Logicstar...
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
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*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:...
***Versions:...
***Features:
o 84-pin PLCC and PQFP packages
o 5V supply requirement (WD76C20)
3.3V supply requirement (WD76C20LV)
o 3.0V battery backup supply for the RTC and 114 byte SRAM (WD76C20)
2.4V battery backup supply for the RTC and 114 byte SRAM
(WD76C20LV)
o Implemented in a low-power, high-performance, 1.25 micron CMOS
technology process
o Floppy Disk Controller (FDC) software transparent power-down mode
with low standby ICC current. FOC features:
- 256 tracks support
- 100% software compatible with NEC 765A
- Integrated high-performance DPLL data separator:
- 125, 250, 300, 500 Kb/sec and 1 Mb/sec data rates
- Option to select 150 Kb/sec FM and 300 Kb/sec MFM data
rates only
- Automatic Write Precompensation:
- Defeat option
- Inner track value of 125 or 187 ns pin selectable
- On chip clock generation:
- 2 TTL clock inputs, or
- Single 16 or 32 MHz crystal circuit and one TTL clock input
- Power Qualified Reset
- Enable PQR in W076C20
- Disable PQR in W076C20LV
- Host interface read/write accesses compatible with 80286
microprocessors at speeds up to 12 MHz with 0 wait states
- Direct floppy disk drive interface - no buffers needed
- 48 mA sink output drivers
- Schmitt Trigger input line receivers
- FDC direct PC XT/AT interface compatibility
- Floppy Control and Operations Registers on chip
- In PC/AT mode, provides required signal qualification to DMA
channel
- IBM BIOS compatible
- Dual-speed spindle drive support
- PS/2 type drive support
o Real Time Clock (RTC) features:
- Software compatible with Motorola MC146818A.
- Internal time base and oscillator circuitry
- Counts seconds, minutes, and hours
- Counts days of the week, date, month, and year
- Time base input for 32.768 KHz square wave
- Time base oscillator for parallel resonant crystals
- Binary or BCD representation of time, calendar, and alarm
- 12- or 24-hour clock with AM and PM in 12-hour mode
- Daylight savings time option
- Automatic leap year compensation
- Interfaced with software as 128 RAM locations
- 114 bytes at general purpose RAM
- Status bit indicates data integrity
- Bus compatible interrupt signals (IRQ)
- Three interrupts are separately software maskable and testable:
- Time-at-day alarm - once-per-second to once-per-day
- Periodic interrupt rates tram 122 us to 500 ms
- End-at-clock update cycle
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
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