[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91
***Info:
GENERAL DESCRIPTION

The  WD76C20 is  a member  of  the WD7600  chip set  which provides  a
cost-effective,  power-efficient   solution  to  PC   systems  design,
especially those  relating to "lap-top" devices. The  set includes the
WD76C10, the WD76C20, and the WD76C30 as shown in Figure 1-1. Together
these chips  provide all necessary  logic to build a  fully integrated
system board for several  varieties of IBM PC/AT compatibles including
systems using 80286, 80386SX, and 80C286 processors.

As  part  of  this  chip  set, the  WD76C20  provides  these  integral
functions:
o Bus Interface Logic
o IDE Interface
o Chip Select Logic
o Floppy Disk Controller
o Real Time Clock
o Suspend/Resume Logic

The Floppy  Disk Controller (FDC) component  provides necessary timing
and signalling between the host  processor peripheral bus and a floppy
disk drive through a cable connector.

The Real Time Clock  component provides calendar and clock information
for the system.

The IDE Interface  controls buffering between the system's  AT Bus and
PC/AT compatible IDE drive interface.

The  Bus  Interface  Logic  controls  buffering of  data  between  the
system's AT Bus and the WD76C20.

The  Chip Select  Logic section  provides decoding  for  selected chip
functions both within the WD76C20 and on the PC/AT motherboard.

Suspend/Resume  Logic provides  support  for chip  set power-down  and
resume sequences.

***Versions:...
***Features:...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...