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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX CPU-Cache Chip Set provides a high performance
solution for servers and high-end desktop systems. This binary
compatible solution has been optimized to provide 50 MHz, zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with the 82495DX/82490DX cache subsystem. It delivers
integer performance of 41 V1.1 Dhrystone MlPs and a SPEC integer
rating of 27.9. The cache subsystem features the 82495DX Cache
Controller and the 82490DX Dual Ported Data RAM. Dual ported buffers
and registers of the 82490DX allow the 82495DX Cache Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.
The CPU-Cache Chip Set offers many features that are ideal for multi-
processor based systems. The Write-Back feature provides efficient
memory bus utilization by reducing bus traffic through eliminating
unnecessary writes to main memory. The CPU-Cache chip set also
supports MESI protocol and monitors the memory bus to guarantee cache
coherency.
The 50 MHz Intel486 DX CPU and 82495DX/82490DX Cache subsystem are
produced on Intel's latest CHMOS V process which features submicron
technology and triple layer metal.
3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip set provides a tightly coupled processing
engine based on the Intel486 microprocessor and a cache subsystem
comprised of the 82495DX cache controller and multiple 82490DX cache
components. Figure 3.1 [see datasheet] diagrams the basic config-
uration.
The cache subsystem provides a gateway between the CPU and the memory
bus. All CPU accesses that can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic. As a result, the cache
chip set reduces memory bus bandwidth to both increase Intel486
processor performance and support efficient multiprocessor systems.
The cache subsystem also decouples the CPU from the memory bus to
provide zero-wait-state operation at high clock frequencies while
allowing relatively slow and inexpensive memories.
The CPU-cache chip set prevents latency and bandwidth bottlenecks
across a variety of uniprocessor and multiprocessor designs. The
processor’s on-chip cache supports a very wide CPU data bus and
high-speed data movement. The second-level cache greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.
3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks:
3.2.1 CPU
The chip set includes a special version of the Intel486DX micropro-
cessor at 50 MHz. The Intel486DX Microprocessor Data Sheet provides
complete component specifications.
3.2.2 CACHE CONTROLLER
The 82495DX cache controller is the main control element for the chip
set. providing tags and line states. and determining cache hits and
misses. The 82495DX executes all CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).
The 82495DX controls the data paths of the 82490DX cache components
for cache hits and misses and furnishes the CPU with needed data. The
controller dynamically adds wait states as needed using the most
recently used (MRU) prediction algorithm.
The 82495DX also performs memory bus snoop operations in shared memory
systems and drives the cycle address and other attributes during
memory bus accesses. Figure 3.2 [see datasheet] diagrams the 82495DX.
3.2.3 CACHE SRAM
Multiple 82490DX cache components provide the cache SRAM and data
path. Each component includes the latches, muxes and logic needed to
work in lock step with the 82495DX to efficiently serve both hit and
miss accesses. The 82490DX components take full advantage of VLSI
silicon flexibility to exceed the capabilities of discrete
implementations. The 82490DX components support zero-wait-state hit
accesses and concurrent CPU and memory bus accesses, and they
replicate MRU bits for autonomous way prediction. During memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.
3.3 Secondary Cache Features
The 82495DX cache controller and 82490DX cache components provide a
unified, software transparent secondary data and instruction cache.
The cache enables a highspeed processor core that provides efficient
performance even when paired with a significantly slower memory bus.
The secondary cache interprets CPU bus cycles and can service most
memory read and write cycles without accessing main memory. I/O and
other special cycles are passed directly to the memory bus. The cache
has a dual-port structure that permits concurrent CPU and memory bus
operation.
The 82495DX cache controller contains the 8K tag entries and logic
needed to support a cache as large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are used to create caches ranging from 128K
to 256K, with or without data parity.
The MBC provides logic needed to interface the CPU, 82495DX and
82490DX to the memory bus. Because the MBC also affects system
performance. its design can be the basis of product differentiation.
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*Western Digital...
**WD8110 System controller for 80386DX/486 <11/30/93
***Notes:...
***Info:
1.0 INTRODUCTION
The WD8110/LV System Controllers are designed to provide a high
performance, single chip system controller supporting all 80486SX,
80486DX. 80386SX and 80386DX CPUs in AT bus based Desktop/
Laptop/Notebook/Pen-based systems.
1.1 DOCUMENT SCOPE
This document describes the function and operation of the WD8110/LV
System Controller devices. It includes the description of external
logic necessary for efficient use of these devices. The WD8110/LV is
also referred to in this document as the System Controller.
1.3 WD8110/LV POWER MANAGEMENT
Power Management Control (PMC) is used for powering down the processor
or peripherals and includes processor stop clock, slow clock, auto-
matic processor clock speed switching modes and CAS before RAS slow
refresh. Suspend and resume is supported and low power DRAM is
refreshed while the processor and other power consuming devices are
turned off. The power drain for the core logic and VGA controller is
less than 2 mA in this mode. Power and clock speed may be controlled
by the Keyboard Controller. transparently to the 80386 or 80486.
The System Activity Monitor (SAM) is a transparent feature that
replaces the functions previously performed by software. It senses
when the system has been idle for a previously programmed period at
time and determines a clean break point in which to perform power down
activities such as suspend.
The system controller also supports System Management Interrupt (SMI)
with complete I/O trapping of up to six separate I/O ranges. Each
range has an independent timer which can generate an SMI after a
programmed period of time during which there was no I/0 access to that
range.
1.3.1 Desktop Applications
The WD8110/LV provides a high performance solution with a flexible
memory controller architecture. including support for five banks of
memory. The WD8110/LV can fully support an external look-aside cache
or a combination primary and secondary cache. This feature makes it
particularly suitable for use with cached microprocessors where it
maintains cache coherency via its built-in bus snooping capability. In
addition. the WD8110/LV supports Video Local Bus Interface (VLBI) for
enhanced graphics performance.
The built-in power management features of the WD8110/LV allows a high
performance yet power efficient desk top solution.
1.3.2 Portable Applications
The WD8110LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation, which
delivers long battery life in a compact footprint. This makes it a
perfect choice for laptop, notebook, pen-based and palmtop computers.
The five bank memory controller on the WD8110LV provides the user with
great flexibility in the selection of 3.3 volt DRAMs to meet system
memory requirements in low voltage platforms. The WD8110LV memory
controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD8ll0/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD8l10/LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. The WD8110 may also be used with the WD7615 Buffer Manager
device and a generic Super I/O chip to implement a low cost desktop
platform. For 3.3 volt applications, the WD8110LV can be used with the
WD76C20ALV and WD76C30ALV, both of which incorporate level translators
(split rail operation). For subnotebook and palmtop type applications,
WD7625LV buffer manager and WD8120LV Super I/O can be added to the
WD8110LV based solution to achieve a very compact footprint.
The WD8110/LV is a fifth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry's leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process. the WD8110/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7855 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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