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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:
o Advanced Interrupt Controller for 32-Bit Operating Systems
o Solutions for Multiprocessing Interrupt Management
o Dynamic Interrupt Distribution for Load Balancing in MP Systems
o Separate Nibble Bus (Interrupt Controller Communications (ICC)
Bus) for interrupt Messages
o Inter-Processor Interrupts
o Various Addressing Schemes - Broadcast, Fixed, Lowest Priority,
etc.
o Compatibility Mode with 8259A
o 32-Bit Internal Registers
o Integrated Timer Support
o 33 MHz Operation
o 123-Lead PQFP Package, Package Type KU
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*Headland/G2...
**HT25 3-volt Core Logic for 386SX c:Dec92
***Info:
The HT25 is the industry’s first 3-Volt single chip core logic with
integrated power management for 386SX based 3-Volt systems. Pro-
grammable power management features give system manufacturers the
flexibility of offering customized system solutions.
GENERAL DESCRIPTION
The HT25 is a PC/AT1M compatible single-chip solution with integrated
power management designed to operate in a 3-Volt system environment.
This highly integrated chip facilitates the design of low power, high
performance portable systems. The HT25 supports 3-Volt 386SX CPUs at
clock speeds up to 25MHz at 2.7V to 3.6V. It supports power
management functions using the System Management Mode (SMM).
Flexible power management is the cornerstone of the HT25. This
approach provides power saving features that can be customized for
product differentiation. Power management features include system
activity monitors and general purpose I/O pins. The HT25 generates
System Management Interrupt (SMI) to process activity information or
when access to powered down peripherals is detected. Further power
savings are achieved through the HT25’s ability to control CPU and NPU
clocks and support for slow refresh and self refresh DRAMs.
The HT25 Memory Controller features BIOS Shadowing, Memory Relocation,
EMS, Page Mode Memory Access and Interleaving. The memory controller
allows memory banks to be reordered to allow more efficient memory in-
terleaving. The HT25 supports 512Kb, le, and 4Mb DRAMs.
The HT25 architecture is optimized for 3-Volt system designs, the SD
bus acknowledge input provides a flexible I/O bus architecture and the
XD bus is buffered directly from the HT25. Further, no external data
bus buffers are required for a closed 3V system.
***Configurations:...
***Features:...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
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