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**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section has been sourced from the
second.
Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE2011 CPU Core Logic for PS/2 Model 30 Compatible c:87
***Info:...
***Versions:...
***Features:
o 100% hardware (register level) and software compatible with IBM
PS/2 Model 30
o Supports 8086, 80C86 and V30 processors
o High performance 10 MHz, zero wait state operation
o One chip includes all CPU core logic for compatible IBM PS/2 Model
30 designs:
- 8237A compatible DMA controller
- 8259A compatible interrupt controller with all PS/2 Model 30
extensions
- 8253 compatible timer
- 8255 compatible PIO port
- Bus control logic
- Clock generation logic
- DRAM control logic
- Address and data buffers
o True Model 30 compatible bidirectional keyboard and mouse ports
o Software selectable CPU clock and DMA wait state
o System board I/O decoder
o Integrated EMS (LIM) support for version 4.0 EMS specification
o Variable RAM configurations: 64K, 256K, 1M DRAM
o Typical Model 30 CPU would consist of FE201l, 8086, 2 crystals,
2 TTL devices and memory
o 132-pin JEDEC Standard package
o Low power CMOS
**FE3400/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:86...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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