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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03
Chips:
[82855PM](MCH) [82801DBM] (ICH4-M)
CPUs: Pentium M, Celeron M
DRAM Types: DDR 200/266/333
Mem Rows: --
DRAM Density: ?
Max Mem: 2GB
ECC/Parity: no
AGP speed: 2x, 4x
Bus Speed: 400 MT/s (100 MHz QDR)
PCI Clock/Bus: 1/3 PCI 2.2
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C683 386/486AWB EISA [no datasheet] ?
***Notes:...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE2011 CPU Core Logic for PS/2 Model 30 Compatible c:87
***Info:
The FE2011 is a single chip implementation of all, core logic needed
to support the 16-bit Intel 8086 Central Processing Unit (CPU) in the
creation of a high performance IBM Personal System/2 Model 30
compatible computer. It replaces nearly 100 components used in prior
8086-based designs.
The FE2011 is 100% hardware, register level, and software compatible
with the PS/2 Model 30. Operating with a 10 MHz clock rate, the FE2011
improves PS/2 Model 30 performance by up to 25%.
Highly Integrated Functional Capabilities
The FE2011 contains all processor and peripheral support logic. It
includes an 8237A compatible Direct Memory Access (DMA) controller, an
8259A interrupt controller with interrupt extension that handles
shared interrupts, an 8253 compatible timer, and 8255 compatible
peripheral I/O port.
It also includes logic for bus control, DRAM control, clock
generation, and the bidirectional keyboard/mouse port.
The FE2011 contains address and data buffers which enable the user to
drive an expansion bus without external drivers. A memory data buffer
and DRAM address multiplexer make it easy to interface directly to
memory.
The FE2011 has built-in extended memory support (the Lotus, Intel and
Microsoft implementation of EMS) that allows access to up to 2.5
Mbytes of memory through use of four page registers.
A system board I/O decoder provides chip select signals for on-board
peripherals: parallel port, serial port, floppy disk controller, hard
disk controller and display adapter.
Implementation Flexibility
The FE2011 supports a flexible memory architecture. It allows usage
of 64K, 256K and 1M DRAM in five different configurations.
With the EMS feature, the FE2011 supports a total of 2.5 Mbytes of
memory consisting of 640K of conventional memory and 1920K of expanded
memory. Operation at 10 MHz requires the use of 100 ns DRAM.
The FE2011 is designed for performance flexibility. It operates at
software selectable CPU clock rates of 7.15 or 9.54 MHz that are
derived from a single 28.636 MHz crystal. The FE2011 can be op-
tionally driven at 8 or 10 MHz using external crystal/oscil-
lators. In addition, the FE2011 supports, software selectable DMA wait
states of zero or one.
Packaging
Manufactured in low-power CMOS, the FE2011 is available in a surface
mount 132-pin JEDEC Standard package.
***Versions:...
***Features:...
**FE3400/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:86...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
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