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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:
The HT18 is an advanced PC/AT compatible, single-chip 80386SX design
solution. This highly integrated single chip allows simple, low cost
system design options while featuring high performance, low power
consumption, and minimum board space requirements. Advanced memory
management features include support for page mode, with 2 or 4-way
interleaving in both pipelined and non-pipelined modes(18A/B only).
Extended Hardware EMS options include dual sets of 32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1, 1 by 4, and 1 by 9 device configurations. Rev C supports 4M
devices, as well. A Shadow RAM option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.
A complete PC/AT compatible system with advanced features may be
implemented with minimal external support logic. The HT18 performs all
CPU and peripheral support functions in a single chip. Integrated
device functions include DMA Controllers, a Memory Mapper, Timers,
Counters, Interrupt Controllers, a Bus Controller and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows for a constant 8MHz Bus clock rate for highest bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin Plastic Quad Flat Pack combining several external buffers
into this space saving solution.
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE2011 CPU Core Logic for PS/2 Model 30 Compatible c:87
***Info:
The FE2011 is a single chip implementation of all, core logic needed
to support the 16-bit Intel 8086 Central Processing Unit (CPU) in the
creation of a high performance IBM Personal System/2 Model 30
compatible computer. It replaces nearly 100 components used in prior
8086-based designs.
The FE2011 is 100% hardware, register level, and software compatible
with the PS/2 Model 30. Operating with a 10 MHz clock rate, the FE2011
improves PS/2 Model 30 performance by up to 25%.
Highly Integrated Functional Capabilities
The FE2011 contains all processor and peripheral support logic. It
includes an 8237A compatible Direct Memory Access (DMA) controller, an
8259A interrupt controller with interrupt extension that handles
shared interrupts, an 8253 compatible timer, and 8255 compatible
peripheral I/O port.
It also includes logic for bus control, DRAM control, clock
generation, and the bidirectional keyboard/mouse port.
The FE2011 contains address and data buffers which enable the user to
drive an expansion bus without external drivers. A memory data buffer
and DRAM address multiplexer make it easy to interface directly to
memory.
The FE2011 has built-in extended memory support (the Lotus, Intel and
Microsoft implementation of EMS) that allows access to up to 2.5
Mbytes of memory through use of four page registers.
A system board I/O decoder provides chip select signals for on-board
peripherals: parallel port, serial port, floppy disk controller, hard
disk controller and display adapter.
Implementation Flexibility
The FE2011 supports a flexible memory architecture. It allows usage
of 64K, 256K and 1M DRAM in five different configurations.
With the EMS feature, the FE2011 supports a total of 2.5 Mbytes of
memory consisting of 640K of conventional memory and 1920K of expanded
memory. Operation at 10 MHz requires the use of 100 ns DRAM.
The FE2011 is designed for performance flexibility. It operates at
software selectable CPU clock rates of 7.15 or 9.54 MHz that are
derived from a single 28.636 MHz crystal. The FE2011 can be op-
tionally driven at 8 or 10 MHz using external crystal/oscil-
lators. In addition, the FE2011 supports, software selectable DMA wait
states of zero or one.
Packaging
Manufactured in low-power CMOS, the FE2011 is available in a surface
mount 132-pin JEDEC Standard package.
***Versions:...
***Features:...
**FE3400/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:86...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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