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**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:...
***Versions:...
***Features:
o   High Performance 
    - Zero Wait State Access on Cache Hit
    - One Clock Bursting 
    - Two-Way Set Associative 
    - Write Protect Attribute Per Tag
    - Start Memory Cycles in Parallel
o   Easy to Use
    - Matches Intel486 Microprocessor Bus Timing
    - Supports Invalidation Cycles
    - Maintains Memory on Writes
o   High Integration
    - Single Chip Tag RAM and Controller
    - No Logic Needed for CPU and Cache Connection
    - Maps Full 4 Gigabyte Address Space
o   Flexible System Configurations
    - Supports 64K or 128K Cache Memory
    - Supports Non-Cacheable Memory Areas

**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*Unresearched:...
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**Video: 
VL16160 "RASTER OP" Graphics Boolean Operation ALU. BITBLT  
VL68C45R/S-23 2Mhz Bus 3MHz Character  CMOS CRT Controller.  
VL68C45R/S-35 3Mhz Bus 5MHz Character  CMOS CRT Controller.  
VL68C45R/S-36 3Mhz Bus 6MHz Character  CMOS CRT Controller.  
VL68C45R/S-38 3Mhz Bus 8MHz Character  CMOS CRT Controller.  
VL82C037 VGA 256K 800x600, 16 colors EGA/CGA/MDA compatible
VL82C164 Quad Raster op ALU
VL82C976 Desktop RISC Graphics Accelerator

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