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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**VL82C114 Combination I/O chip                                      ?
***Info:
The  VL82C114  Combination  I/O  chip,  when  used  with  VLSI  System
Controller chips, allows designers  to implement a very cost-effective
minimum  chip  count  motherboard.   This  chip  combines  a  keyboard
controller and  a real-time clock with the  address registers/ latches
and  buffers  which  are  normally  required  in  ISA  bus  compatible
systems.  The VL82C114 features  an AT-compatible  keyboard controller
with integrated PS/2 mouse support and a 146818A-compatible real-time
clock. The  VL82C114 also has  114 additional bytes  of battery-backed
CMOS RAM for  use in extended system setup.  In addition, the VL82C114
provides support for processors with write-back cache controllers.

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