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**440 series:
***440FX (Natoma) 05/06/96...
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**SL82C550 'Rossini' Pentium [no datasheet] c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
The Symphony "Rossini" Chipset (Symphony Labs: 10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates with up to 66 MHz external clock rates, up to two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache, EDO RAM, and does dual-port busmastering IDE. It will,
apparently, adjust the voltages to its various (CPU, PCI, cache, RAM)
buses to suit their requirements, and will control up to six PCI
masters. It consists of the SL82C551 cache/memory controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C107 SCAMP Combination I/O chip ?
***Info:
The VL82C107 SCAMP Combination I/O chip when used with other VLSI
SCAMP chips, allows designers to implement a very cost-effective
minimum chip count motherboard. This chip combines a keyboard
controller, a real-time clock with the address latches/buffers and DMA
acknowledge decodes which are normally required in SCAMP- based
systems. Additionally, the VL82C107 contains the circuity necessary to
interface PC memory cards to the system or provide the chip select and
control signals for an external VL16C552 UART I/O device, FDC, and IDE
interface.
***Versions:...
***Features:...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
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**Not sure if they actually exist...
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