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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:
o Two-Way, Set Associative, Secondary Cache for i860 XP
Microprocessor
o 50 MHz "No Glue" Interface with CPU
o Configurable
- Cache Size 256 or 512 Kbytes
- Line Width 32, 64 or 128 Bytes
- Memory Bus Width 64 or 128 Bits
o Dual-Ported Structure Permits Simultaneous Operations on CPU and
Memory Buses
o Efficient MRU Way Prediction
- Zero Wait States on MRU Hit
- One Walt State on MRU Miss
o Dynamically Selectable Update Policies
- Write-Through
- Write-Once
- Write-Back
o MESI Cache Consistency Protocol
o Hardware Cache Snooping
o Maintains Consistency with Primary Cache via Inclusion Principle
o Flexible User-Implemented Memory Interface Enables Wide Range of
Product Differentiation
- Clocked or Strobed
- Synchronous or Asynchronous
- Plpelining
- Memory Bus Protocol
o 82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid
Array Package
o 82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack
Package
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP System/Power Management Controller (cached) c:93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C425 486 Cache controller ?
***Info:
The VL82C425 Cache Controller provides a low-cost direct map,
look-aside write-back cache option for use with the VL82C486 System
Controller. It supports from 64 KB to 1 MB cache sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache size and tag option selected. the cache line size is 16
bytes (four double words).
one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the data. Increased read performance is obtained by using two
banks which allow interleaved accesses during burst read cycles.
only one 8-bit or 9-bit (optional) tag SRAM is required to hold the
upper memory address bits and the dirty bit. The number of tag SRAM
locations required is equal to the size of the data cache (in bytes)
divided by 16.
***Versions:...
***Features:...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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