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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:...
***Configurations:...
***Features:
o Highly Integrated, Single Chip 80386SX AT Compatible Solution
o Special Multiple Context Hardware EMS Support (LIM 4.0 compatible)
using 2 sets of 32 EMS Registers
o Single or Dual BIOS
o Shadow RAM support over entire C0000 to DFFFF Address range in 16K
increments, E0000 to FFFFF in 64K increments
o Page Mode and 2-way Interleaving
o Supports up to 12MHz AT Bus Clock
o High Performance Muxed DRAM Interleave
o Programmable DRAM timing
o Asynchronous AT Bus Clock
o Three-State Test Mode
o 16-Bit ROM BIOS Support
HT 18A/B Special Features
o 16 and 20 MHz CPU Clock Speeds
o Supports up to 8M CPU Memory using combinations of 64K, 256K and
1M Devices
o 4 Bank, 4-way Interleave Mode
HT18C/25MHz Special Features
o 16, 20 and 25MHz CPU Clock Speeds
o Supports up to 20M with EMS CPU Memory using combinations of 256K,
1M and 4M Devices
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C425 486 Cache controller ?
***Info:
The VL82C425 Cache Controller provides a low-cost direct map,
look-aside write-back cache option for use with the VL82C486 System
Controller. It supports from 64 KB to 1 MB cache sizes. It can cache
from the first 8 MB to the first 256 MB of on-board DRAM, depending on
the cache size and tag option selected. the cache line size is 16
bytes (four double words).
one or two 32-bit wide banks of asynchronous cache SRAM may be used to
hold the data. Increased read performance is obtained by using two
banks which allow interleaved accesses during burst read cycles.
only one 8-bit or 9-bit (optional) tag SRAM is required to hold the
upper memory address bits and the dirty bit. The number of tag SRAM
locations required is equal to the size of the data cache (in bytes)
divided by 16.
***Versions:...
***Features:...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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