[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99
***Info:...
***Configurations...
***Features:...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?
***Info:
VLSI Technology, Inc.'s VL82C380 is a highly integrated 32-bit
single-chip PC/AT controller with on-chip cache controller designed
for use in 386DX-based ISA systems operating at up to 40 MHz. Its
cache controller is designed with a look-aside, write- back
architecture for increased write performance as well as read
performance. Full coherency is maintained during DMA/Master Mode
cycles.
The VL82C380 is a highly integration solution. A complete system can
be implemented using only the CPU, BIOS, DRAM, VL82C380, VL82C113A
Combination I/O and 3 SSI TTL's, plus optional TAG and Data SRAMs.
Tag SRAMs can be either 8- or 9-bit (7- or 8-bit tag plus a dirty
bit). Dirty and Valid bits are optional, each may be disabled in order
to increase cacheable DRAM range. The Dirty bit, when used, indicates
that the cache has been updated but not the corresponding locations in
DRAM. The Valid bit, when used, indicates that both the cache and
corresponding DRAM locations have been updated.
Only on-board DRAM is cached, this prevents coherency issues
associated with caching system memory in the USA bus. Full coherency
is maintained during DMA/Master mode cycles, so flushing and
invalidating operations are unnecessary. set-up/sizing mode
(programmable) provides direct access to the cache data SRAMs.
The Memory Controller logic is capable of accessing up to 64 MB. There
can be up to 4 banks of 256K, 1M, or 4M DRAMs used in the system. The
VL82C380 can drive two banks without external buffering. Built-in
page-mode operations and up to 2-way interleaving allow the PC
designer to maximize system performance using low-cost
DRAMs. Programmable DRAM timing is provided for RAS precharge, RAS to
CAS delay, and CAS pulse width.
***Configuration:...
***Features:
o Highly integrated system solution using VL82C380 single-chip
ISA controller, VL82C113A Combination I/O chip and 3 TTLs
o Supports one- or two-bank write-back cache
- External TAGs
- 32 Kbyte to 1 Mbyte cache size
- 0 or 1 wait state writes
- Separate dirty RAM not required; first write to clean, valid
line sets dirty bit
o Caches main system DRAM only
o Maintains full coherency during DMA/MASTER mode cycles
o Optional remap of video and hard disk ROM BIOS onto motherboard,
allowing use of single BIOS ROM
o Optional bus acceleration for video accesses, with programmable
address regions
o Software-configurable
o Utilizes proven 8254, 8237, 8259 megacalls used in all previous
VLSI Technology PC/AT chipsets
o High-performance memory controller:
- One wait state red up to 33 MHz, Zero wait state reads up to
40 MHz
- Automatic configuring of Bank start address
- Each bank individually configurable for any supported DRAM type
- shadow RAM support form 640K to 1M in 16K segments
- Staggered refresh reduces power supply peak currents
- Decoupled-mode refresh improves performance
- Programmable refresh frequency for support of slow-refresh DRAMs
- Up to 64 Mbytes of motherboard memory in one to four banks using
256K, 1M, and/or 4Mbit DRAM, all motherboard memory is cacheable
- Direct-drive up to 2 banks (32 Mbyte) of motherboard memory
- Two-way page mode interleave
- Supports 32-bit ini-interleaved or interleaved configurations
- Programmable RAS/CAS timing supported for Cycle-start, Trp,
Trcd, and Tacs
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved