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*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX CPU-Cache Chip Set provides a high performance
solution for servers and high-end desktop systems. This binary
compatible solution has been optimized to provide 50 MHz, zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with the 82495DX/82490DX cache subsystem. It delivers
integer performance of 41 V1.1 Dhrystone MlPs and a SPEC integer
rating of 27.9. The cache subsystem features the 82495DX Cache
Controller and the 82490DX Dual Ported Data RAM. Dual ported buffers
and registers of the 82490DX allow the 82495DX Cache Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.
The CPU-Cache Chip Set offers many features that are ideal for multi-
processor based systems. The Write-Back feature provides efficient
memory bus utilization by reducing bus traffic through eliminating
unnecessary writes to main memory. The CPU-Cache chip set also
supports MESI protocol and monitors the memory bus to guarantee cache
coherency.
The 50 MHz Intel486 DX CPU and 82495DX/82490DX Cache subsystem are
produced on Intel's latest CHMOS V process which features submicron
technology and triple layer metal.
3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip set provides a tightly coupled processing
engine based on the Intel486 microprocessor and a cache subsystem
comprised of the 82495DX cache controller and multiple 82490DX cache
components. Figure 3.1 [see datasheet] diagrams the basic config-
uration.
The cache subsystem provides a gateway between the CPU and the memory
bus. All CPU accesses that can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic. As a result, the cache
chip set reduces memory bus bandwidth to both increase Intel486
processor performance and support efficient multiprocessor systems.
The cache subsystem also decouples the CPU from the memory bus to
provide zero-wait-state operation at high clock frequencies while
allowing relatively slow and inexpensive memories.
The CPU-cache chip set prevents latency and bandwidth bottlenecks
across a variety of uniprocessor and multiprocessor designs. The
processor’s on-chip cache supports a very wide CPU data bus and
high-speed data movement. The second-level cache greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.
3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks:
3.2.1 CPU
The chip set includes a special version of the Intel486DX micropro-
cessor at 50 MHz. The Intel486DX Microprocessor Data Sheet provides
complete component specifications.
3.2.2 CACHE CONTROLLER
The 82495DX cache controller is the main control element for the chip
set. providing tags and line states. and determining cache hits and
misses. The 82495DX executes all CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).
The 82495DX controls the data paths of the 82490DX cache components
for cache hits and misses and furnishes the CPU with needed data. The
controller dynamically adds wait states as needed using the most
recently used (MRU) prediction algorithm.
The 82495DX also performs memory bus snoop operations in shared memory
systems and drives the cycle address and other attributes during
memory bus accesses. Figure 3.2 [see datasheet] diagrams the 82495DX.
3.2.3 CACHE SRAM
Multiple 82490DX cache components provide the cache SRAM and data
path. Each component includes the latches, muxes and logic needed to
work in lock step with the 82495DX to efficiently serve both hit and
miss accesses. The 82490DX components take full advantage of VLSI
silicon flexibility to exceed the capabilities of discrete
implementations. The 82490DX components support zero-wait-state hit
accesses and concurrent CPU and memory bus accesses, and they
replicate MRU bits for autonomous way prediction. During memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.
3.3 Secondary Cache Features
The 82495DX cache controller and 82490DX cache components provide a
unified, software transparent secondary data and instruction cache.
The cache enables a highspeed processor core that provides efficient
performance even when paired with a significantly slower memory bus.
The secondary cache interprets CPU bus cycles and can service most
memory read and write cycles without accessing main memory. I/O and
other special cycles are passed directly to the memory bus. The cache
has a dual-port structure that permits concurrent CPU and memory bus
operation.
The 82495DX cache controller contains the 8K tag entries and logic
needed to support a cache as large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are used to create caches ranging from 128K
to 256K, with or without data parity.
The MBC provides logic needed to interface the CPU, 82495DX and
82490DX to the memory bus. Because the MBC also affects system
performance. its design can be the basis of product differentiation.
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5 A.G.P./VGA chipset, SiS530/5595, provides a high performance/
cost index Desktop/Mobile solution for the Intel Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and other compatible Pentium CPU with 3D
A.G.P. VGA system.
The Host, PCI, 3D A.G.P. Video/Graphics & Memory Controller, SiS530
integrates the Host- to-PCI bridge, the PCI interface, the L2 cache
controller, the DRAM controller, the high performance hardware 2D/3D
VGA controller, and the PCI IDE controller.
The Host interface supports Synchronous/Asynchronous Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.
The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller can support SDRAM memory up to 1.5 GBytes with three
double-sided SDRAM DIMMs configuration. The cacheable DRAM sizes
support up to 256 MBytes.
The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function that support the data transfer rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.
The A.G.P. internal interface is supported for integrated H/W 3D VGA
controller. The integrated VGA controller is a high performance and
targeted at 3D graphics application. In addition, the integrated 3D
Video/Graphics controller adopts the 64bits 100MHz host bus interface
high technology to improve the performance eminently. To cost-
effective the PC system, the share system memory architecture will be
adopted and it can flexibly using the 2MB, 4MB and 8MB frame buffer
size from programming the system BIOS. [something got confused in
translation there didn't it?] To enhance the system performance,
SiS530 also supports the local frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.
In addition to provide the standard interface for CRT monitors, it
also provides the Digital Flat Panel Port (DFP) for a standard
interface between a personal computer and a digital flat panel
monitor. This port allows a host computer to connect directly to an
external flat panel monitor without the need for analog-to-digital
conversion found in most flat panel monitors today. As for DVD
solution, the integrated 3D VGA controller also support DVD H/W
accelerator to improve the DVD playback performance.
The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the
DDMA, PC/PCI DMA and Serial IRQ capability, the ACPI/Legacy PMU, the
Data Acquisition Interface, the Universal Serial Bus host/hub
interface, and the ISA bus interface which contains the ISA bus
controller, the DMA controllers, the interrupt controllers, the Timers
and the Real Time Clock (RTC). It also integrates the Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function for users to power on system by entering the hot key or
password from keyboard. The built-in USB controller, which is fully
compliant to OHCI (Open Host Controller Interface), provides two USB
ports capable of running full/low speed USB devices. The Data
Acquisition Interface offers the ability of monitoring and reporting
the environmental condition of the PC. It could monitor 5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.
In addition, SiS5595 also supports ACPI function to meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment, it can support power-management timer, Power button,
Real-time clock alarm wake up, more sleeping state, ACPI LED for
sleeping and working state, LAN wake up, Modem Ring In wake up, and
OnNow initiative function.
***Configurations:...
***Features:...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?
***Info:...
***Configuration:...
***Features:...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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