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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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*Unresearched:...
*VIA...
*VLSI...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?
***Info:
VLSI Technology, Inc.'s VL82C380 is a highly integrated 32-bit
single-chip PC/AT controller with on-chip cache controller designed
for use in 386DX-based ISA systems operating at up to 40 MHz. Its
cache controller is designed with a look-aside, write- back
architecture for increased write performance as well as read
performance. Full coherency is maintained during DMA/Master Mode
cycles.
The VL82C380 is a highly integration solution. A complete system can
be implemented using only the CPU, BIOS, DRAM, VL82C380, VL82C113A
Combination I/O and 3 SSI TTL's, plus optional TAG and Data SRAMs.
Tag SRAMs can be either 8- or 9-bit (7- or 8-bit tag plus a dirty
bit). Dirty and Valid bits are optional, each may be disabled in order
to increase cacheable DRAM range. The Dirty bit, when used, indicates
that the cache has been updated but not the corresponding locations in
DRAM. The Valid bit, when used, indicates that both the cache and
corresponding DRAM locations have been updated.
Only on-board DRAM is cached, this prevents coherency issues
associated with caching system memory in the USA bus. Full coherency
is maintained during DMA/Master mode cycles, so flushing and
invalidating operations are unnecessary. set-up/sizing mode
(programmable) provides direct access to the cache data SRAMs.
The Memory Controller logic is capable of accessing up to 64 MB. There
can be up to 4 banks of 256K, 1M, or 4M DRAMs used in the system. The
VL82C380 can drive two banks without external buffering. Built-in
page-mode operations and up to 2-way interleaving allow the PC
designer to maximize system performance using low-cost
DRAMs. Programmable DRAM timing is provided for RAS precharge, RAS to
CAS delay, and CAS pulse width.
***Configuration:...
***Features:...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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