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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C700 FireStar c:97
***Info:...
***Configurations:...
***Features:
PCI Bus
o PCI supports sustained X-1-1-1 bursts, even to DRAM through an
innovative mechanism. PCI operation can be concurrent with
CPU/L2 cache and IDE operations.
o PCI clock generation eliminates the need for external PCI clock
buffers in many designs and allows the PCI bus to be effectively
power-managed.
o 3.3V or 5.0V PCI is supported on the FireStar PCI bus. If FireStar
is configured for 3.3V operation, 5.0V-only PCI plug-in cards and
docking stations can still be supported through a bridge device
such as OPTi's 820824 Cardbus Controller/Docking Solution, whose
prefetch and post-write buffers off-load operations from the
primary PCI bus.
DRAM Controller
o Provides BIOS with the means to automatically detect the DRAM type
in use on each bank, whether fast page mode, EDO, or synchronous
DRAM, allowing BIOS routines to efficiently program DRAM
operation.
ISA Bus
o A full ISA bus is directly provided to support the keyboard
controller, BIOS ROM, and Compact ISA peripheral devices for local
ISA support with no TTL. When reduced ISA operation is selected,
other FireStar pins become available for general purpose use.
Bus Mastering IDE
o FireStar supports two bus mastering IDE channels that function
concurrently with operations on the CPU/L2 cache interface and PCI
interface. Up to four drives are supported.
o An emulated bus mastering IDE feature allows IDE drives that are
not commonly available as bus mastering devices, such as CD-ROM
drives, to act as bus mastering drives. For example, a CD-ROM
drive can transfer video data to DRAM while the CPU is
decompressing the data and sending it to the graphics controller.
Thermal Management
o Fail-safe thermal management incorporates feedback logic that
requires a very inexpensive external sensor circuit.
o Hardware monitors temperature directly and reliably, while the
fail-safe aspect of the circuitry ensures that sensor component
failure will automatically inhibit CPU clocking to prevent
overheating.
o SMM code will be able to read (and display if desired) actual CPU
temperature.
ACPI Implementation
o Microsoft Advanced Configuration and Power Interface (ACPI) is
being implemented in the FireStar silicon. ACPI is a standard
register interface for power management function jointly developed
by Microsoft, Intel, and Toshiba.
Miscellaneous
o The standard version of the chip can run at 3.3V, up to 66MHz on
the CPU bus.
o A new Context Save Mode feature allows chip registers to be saved
and restored more efficiently than ever before, requiring less SMM
code and storage space.
o The OPTi Viper-N+ Power Management Unit is used, maintaining
backward compatibility down to the register level with previously
written support firmware.
o Serial IRQs are supported as an option for interrupts on PCI.
o Known devices in the system can be positively decoded on the PCI
bus, eliminating the delay for subtractive decode and improving
the efficiency of ISA operations.
o ISA bus cycle speed can be individually controlled to certain ISA
device groups.
o Simple logic gate functions can be assigned to unused pins to
eliminate the need for external TTL. Pin programming is far more
flexible than ever possible on any other chip.
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?
***Info:
The VL82C316 is a true single chip AT, high-performance controller for
386SX-based PC/AT systems. The VL82C316 is intended primarily for low-
power applications requiring a high degree of integration (e.g.
notebooks). However, the VL82C316 is also an excellent choice for
high- integration, low-cost desktop systems running up to 33 MHZ.
The VL82C316 includes the dual 82C37 DMA controllers, dual 82C59A
programmable interrupt controllers, 82C54 programmable interval timer,
82284 clock and ready generator, 82288 bus controller, 8042 keyboard
controller, and 146818A-compatible real-time clock. Also included is
the logic for SMM (system Management Mode) control, address/data bus
control, memory control, shutdown, refresh generation and refresh/DMA
arbitration.
The controller also includes the following:
o AMD and Cyrix compatible SMM and I/O Break interface
o Complete ISA bus interface logic
o Integrated power management features
o Supports slow and self-refresh DRAM
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Optional parity checking logic
o Optional parity generation logic
The VL82C316 supports 387SX-compatible numeric coprocessors including
versions that support slow and stop clock operation.
The memory controller logic is capable of accessing up to 16 MB. There
can be up to four banks of 256K, 1M, or 4M attached in the system or
eight banks of 512K x 8 DRAMS. The VL82C316 can drive the full
compliment of DRAM banks without external buffering. It features
Built-in Page Mode operation. This, along with two-way interleaving
allow the PC designer to maximize system performance using low-cost
DRAMs. Support is also included for zero, one, or two wait state
operation of system DRAM.
Shadowing features are supported on 16k boundaries between C0000h and
DFFFFh, and on 32K boundaries between A0000h and BFFFFh, and between
E0000h and FFFFFh. Simultaneous shadowed ROM, and direct system board
access is possible in a non-overlapping fashion throughout this memory
space. Control over four access options is provided. The options are:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
The VL82C316 handles system board refresh directly and controls the
timing of slot bus refresh. Refresh is performed in the standard
PC/AT-compatible Mode where on- and off-board refreshes are performed
synchronously. Refreshes are staggered to minimize power supply
loading and attenuate noise on the VDD and ground pins. In the
VL82C316, refresh can be programmed to support CAS-before-RAS refresh
operation or standard RAS-only refresh operation, self-refresh, or no
refresh operation. The VL82C316 supports the PC/AT standard refresh
period of 15.625 plus 125 us or 250 us slow refresh options. When the
Suspend Mode is active, the real-time clock's 32 kHz oscillator is
used as the timing reference for absolute minimum power
dissipation. Self-refresh is possible only in the Suspend Mode. DRAM
accesses are not possible in this mode of operation. When
self-refresh is active, it is only enabled when the Suspend Mode is
also active. Otherwise, CAS-before-RAS refresh is used.
A 146818A-compatible real-time clock (RTC) is provided that supports
battery voltages down to 2.4 volt standard. It also includes 128 extra
battery-backed RAM locations (178 total) for operating system and
power-management support. The base address of the RTC is
programmable, but defaults to the PC standard address. the hardware
supports an external RTC. It may be used with the internal RTC or by
itself by disabling the internal RTC.
An internal keyboard controller replaces the standard 8042 required in
a standard PC environment. It provides a keyboard and PS/2 mouse
interface. As an option, the internal keyboard controller can be
disabled allowing use of an external controller.
The 387SX is supported. A software coprocessor reset does not leave a
387SX in the same state as does the reset of a 287. The VL82C316 can
be programmed to disable these software resets if problems arise.
The interrupt controller logic consists of two 82C509A megacells with
eight interrupt request lines each for a total of 16 interrupts. The
two megacells are cascaded internally and two of the interrupt request
inputs are connected to internal circuitry allowing a total of 13
external interrupt requests. There is a special programmable logic
included in the VL82C316 which allows glitch-free inputs on all the
interrupt request pins.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
The DMA controllers are 82C37A compatible. The DMAs control data
transfers bet- ween an I/O channel and on- or off-board memory. DMA
can transfer data over the full 16 MB range available. There are
internal latches provided for latching the middle address bits output
by the 82C37A megacells on the data bus, and 74LS612 memory mappers
are provided to generate the upper address bits. An optional low-
power DMA mode is available. in this mode, the DMA clocks are stopped
except when DMA accesses are in progress.
The VL82C316 can be programmed for asynchronous or synchronous
operation of the AT bus.
The VL82C316 also performs all the data buffer control functions
required. Under the control of the CPU, the VL82C316 chip routes data
to and from the CPU's D bus and the slots (SD bus). The parity is
checked for D bus DRAM read operations. The data is latched for
synchronization with the CPU. Parity OS generated for all data written
to the D bus. The parity function may be optionally disabled except
when 512K x 8 DRAM memory maps are used. In this case, parity is not
an available option.
***Configurations:...
***Features:...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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