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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?
***Info:...
***Configurations:...
***Features:
o Compatible with 386SX-based PC/AT compatible systems
o Up to 33 MHz system clock
o Replaces 11 peripheral devices on the motherboard:
- Two 82C37A DMA controllers
- 74LS612 memory mapper
- Two 82C59A interrupt controllers
- 82C54 timer
- 82284 clock generator and ready interface
- 82288 bus controller
- Keyboard Controller
- Real-time clock
o Includes:
- Memory/refresh controller
- Port B and NMI logic
- Bus steering logic
- Parity generation checking logic
- Turbo Mode control logic
- Staggered refresh to minimize power supply load variations
- Three-state control pin for board level testability
o Supports:
- Up to 16 MB system memory
- PCMCIA 1.0 IC Memory Card mapping logic
- VL82C325 (SX) Cache Controller compatible
- Four 16- or 18-bit wide banks of 256K, 1M, or 4M DRAM or eight
- 16-bit wide banks of 512K x 8 DRAM
- Shadow RAM in 640K to 1M range
- 387SX numeric coprocessors
- 8- or 16-bit wide BIOS ROMs
- Synchronous or asynchronous slot bus operation up to 16 MHz
- Relocation of video and slot ROMs
o Power saving features include:
- Sleep and Suspend Modes
- Slow DRAM refresh
- CAS-before-RAS and Self-Refresh
- Sleep Mode refresh switch to 32 kHz clock
- Leakage Control in Stop Clock or Suspend Mode
- CPU on or off option in Suspend Mode
- Low-power page interleave memory mode
- Fully static operation
- DMA power management mode
- Full SMM (system Management Mode) and I/O breal support
- Supports standard Sleep Mode for interface to the VL82C323
Power Management Unit (PMU) or other third party PMUs
- Programmable, extendable peripheral cycle
- Disable software coprocessor reset option
- Option for automatic bus speed-up on video or PCMCIA accesses
- Full support for local bus peripherals
- Separate power pins for ISA bus signals allows ISA to be powered
down independently of other interfaces
o Other advanced features:
- Programmable I/O decode for 10 or 16-bit addresses
- Hardware configurable setup to minimize custom BIOS requirements
- Programmable drive current to reduce ringing on DRAM
o 0.8-micron CMOS technology
o 208-lead metric quad flat pack (MQFP)
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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