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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX CPU-Cache Chip Set provides a high performance
solution for servers and high-end desktop systems. This binary
compatible solution has been optimized to provide 50 MHz, zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with the 82495DX/82490DX cache subsystem. It delivers
integer performance of 41 V1.1 Dhrystone MlPs and a SPEC integer
rating of 27.9. The cache subsystem features the 82495DX Cache
Controller and the 82490DX Dual Ported Data RAM. Dual ported buffers
and registers of the 82490DX allow the 82495DX Cache Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.
The CPU-Cache Chip Set offers many features that are ideal for multi-
processor based systems. The Write-Back feature provides efficient
memory bus utilization by reducing bus traffic through eliminating
unnecessary writes to main memory. The CPU-Cache chip set also
supports MESI protocol and monitors the memory bus to guarantee cache
coherency.
The 50 MHz Intel486 DX CPU and 82495DX/82490DX Cache subsystem are
produced on Intel's latest CHMOS V process which features submicron
technology and triple layer metal.
3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip set provides a tightly coupled processing
engine based on the Intel486 microprocessor and a cache subsystem
comprised of the 82495DX cache controller and multiple 82490DX cache
components. Figure 3.1 [see datasheet] diagrams the basic config-
uration.
The cache subsystem provides a gateway between the CPU and the memory
bus. All CPU accesses that can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic. As a result, the cache
chip set reduces memory bus bandwidth to both increase Intel486
processor performance and support efficient multiprocessor systems.
The cache subsystem also decouples the CPU from the memory bus to
provide zero-wait-state operation at high clock frequencies while
allowing relatively slow and inexpensive memories.
The CPU-cache chip set prevents latency and bandwidth bottlenecks
across a variety of uniprocessor and multiprocessor designs. The
processor’s on-chip cache supports a very wide CPU data bus and
high-speed data movement. The second-level cache greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.
3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks:
3.2.1 CPU
The chip set includes a special version of the Intel486DX micropro-
cessor at 50 MHz. The Intel486DX Microprocessor Data Sheet provides
complete component specifications.
3.2.2 CACHE CONTROLLER
The 82495DX cache controller is the main control element for the chip
set. providing tags and line states. and determining cache hits and
misses. The 82495DX executes all CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).
The 82495DX controls the data paths of the 82490DX cache components
for cache hits and misses and furnishes the CPU with needed data. The
controller dynamically adds wait states as needed using the most
recently used (MRU) prediction algorithm.
The 82495DX also performs memory bus snoop operations in shared memory
systems and drives the cycle address and other attributes during
memory bus accesses. Figure 3.2 [see datasheet] diagrams the 82495DX.
3.2.3 CACHE SRAM
Multiple 82490DX cache components provide the cache SRAM and data
path. Each component includes the latches, muxes and logic needed to
work in lock step with the 82495DX to efficiently serve both hit and
miss accesses. The 82490DX components take full advantage of VLSI
silicon flexibility to exceed the capabilities of discrete
implementations. The 82490DX components support zero-wait-state hit
accesses and concurrent CPU and memory bus accesses, and they
replicate MRU bits for autonomous way prediction. During memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.
3.3 Secondary Cache Features
The 82495DX cache controller and 82490DX cache components provide a
unified, software transparent secondary data and instruction cache.
The cache enables a highspeed processor core that provides efficient
performance even when paired with a significantly slower memory bus.
The secondary cache interprets CPU bus cycles and can service most
memory read and write cycles without accessing main memory. I/O and
other special cycles are passed directly to the memory bus. The cache
has a dual-port structure that permits concurrent CPU and memory bus
operation.
The 82495DX cache controller contains the 8K tag entries and logic
needed to support a cache as large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are used to create caches ranging from 128K
to 256K, with or without data parity.
The MBC provides logic needed to interface the CPU, 82495DX and
82490DX to the memory bus. Because the MBC also affects system
performance. its design can be the basis of product differentiation.
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:
The 82C281/2 is a highly integrated AT system logic VLSI for high end
386 Sx AT systems. It integrates the logic for local DRAM control, AT
bus control, cache memory control, and data bus control and is
designed for systems running at 16MHz, 20MHz, and 25MHz.
A high performance, compact 386 Sx/AT system can be implemented easily
with 82C281/2 and standard peripheral controllers like the 82C206 or
the VLSI 82C100 plus Dallas Semiconductor DS1287.
2 System Operation
The following sections describe the detailed system operations of the
82C281 /2 based Sx-AT design.
2.1 Reset
The power good (PWRGD) signal from power supply drives the system into
the initial state when it is asserted low. The 82C281/2 forces CPURST,
SYSRST, and NPRST high as soon as PWRGD becomes inactive. When the
PWRGD is high, the chip deactivates the CPURST, SYSRST, and NPRST
after 128 CLK2 cycles.
2.2 Cache Interface
The 82028112 cache control unit monitors the HIT# pin and the internal
NCA# signals to determine if it is a cache hit or cache miss
cycle. During the cache read miss cycle, the cache controller asserts
TAGWE# to update the TAG RAM, CAWE# is also asserted to update the
cache data memory.
The A1 CNT output will be forced high then low to toggle CPU address
bit 1 to cache data memory to achieve the prefetch.
During cache write hit cycles, the cache controller asserts the CAWE#
signal to update the cache data memory.
2.3 Local DRAM Interfaces
Local DRAM is located on the CPU local data bus and is buffered by a
F244 and F373 buffer. During CPU read cycles data is routed from main
memory to CPU through F244’s Which are controled by LMRD#. During CPU
write cycles, data is latched by F373 latches with the PDLTH signal
from the 82C281/2 while DWE# controls the transceivers' enable. The
main memory subsystem asserts the LMRD# while CPU, DMA, and external
master card reads the local DRAM. DWE# is asserted during local DRAM
memory write.
For local memory read cycles, the memory controller reads two bytes at
a time. The read data passes into 82C281/2 where the parity checking
function is executed.
For the local memory write cycles, the data bus control unit generates
the parity bits to be stored into the local DRAM.
2.4 System BIOS ROM
If the system BIOS ROM is not shadowed, the ROM cycles are treated as
AT cycles. The system designer can put the ROM on the XD bus as an
8-bit slave or SD bus as a 16-Bit slave.
For a 16-bit slave, ROMCS# is connected to M16# through an open
collector driver such as a 7407, the 82C281/2 monitors M16# to
determine the width of the ROM data path.
2.5 I/O Ports located on the XD bus
For l/O ports located on the XD bus, the XDIR# is activated. I/O ports
0F0H - 0FFH are reserved for the coprocessor.
2.6 Refresh Cycles
The AT bus control unit arbitrates the hold request from 82C206 and
the refresh request from 82C281/2 internal, then decides which is the
next owner of the bus once the CPU relinquishes it. The refresh
request generated internally by 82C281/2 can be programmed as every
15.9 micro-seconds or every 95.5 micro-seconds for slow refresh
DRAM. lf the bus is granted for refresh cycles, the AT bus control
unit asserts RFSH# and MEMRD# commands and also generates the refresh
address.
2.7 DMA Cycles
The hold request from the 82C206 initiates DMA/Master transfers. The
82C281/2 performs the arbitration between HRQ and refresh
request. After the CPU acknowledges by asserting HLDA, and DMA request
wins the arbitration, the 82C281/2 sends HLDA1 to the 82C206
acknowledging the request. The 820206 then asserts DMA16# and
activates ADS16# to start 16-bit DMA transfers, or asserts DMA8# and
activates ADS8# to start 8-bit DMA transfers.
***Configurations:...
***Features:...
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C310 SCAMP-LT ?
***Info:...
***Configurations:...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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