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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
***Versions:...
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*HMC (Hulon Microelectronics)...
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*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?
***Info:
The TOPCAT 286/386SX chip set from VLSI Technology, Inc. is a very
high-integration chip set for use in the design of PC/AT-compatible
based systems. This chip set is intended for use in 80286 or 80386SX
microprocessor-based systems with clock speeds from 12 to 25 MHz.
The TOPCAT 286/386SX chip set provides design engineers with a very
flexible, high- performance, low-cost board design solution for IBM
PC/AT-compatible desktop, laptop, portable, and hand-held computers.
The TOPCAT 286/386SX two-device chip set has been designed with the
highest integration consistent with economic and reliable system
design. It provides a complete board design using only four non-memory
devices including the microprocessor.
VLSI's TOPCAT 286/386SX chip set was designed with seven goals.
o Lowest system board cost
o Smallest board area requirement
o Highest performance in both cached and non-cached systems
o Single board design for:
- 12 to 15 MHz operation
- Cache or non-cache
- 512K byte to 32M byte memory using 256K, 1M and 4M bit DRAM
- Laptop or desktop applications
o Full hardware LIM EMS 4.0 support for highest possible performance
o Built-in, in-circuit test modes for easy board level testing
o The VL82C320A interfaces to the VL82C335 "look-aside" Cache
Controller
With VLSI's TOPCAT 286/386SX chip set, you can be assured that your
high-performance system design needs are met.
The VL82C320/VL82C320A contains the System Control and the Data
Buffering functions in a 160-lead quad flatpack. The System Controller
is designed to perform in 80286- and 80386SX-based systems with clock
speeds of 25 MHZ and below, and peripheral bus speeds up to 12MHz. The
System Controller functions are highly programmable via a set of
internal configuration registers. Defaults on reset for the
configuration registers mimic the compatibility requirements of the
original IBM PC/AT as closely as possible. The power-up defaults
allow any possible configuration of the system to boot at the CPU's
rated speed.
The System Controller handles system board refresh directly and
controls the timing of slot bus refresh that is actually performed by
the VL82C331 ISA Bus Controller. Refresh may be performed in coupled
or decoupled mode. The former method is the standard PS/AT- compatible
mode where on- and off-board refreshes are independent. Both may be
programmed for independent, slower than normal rates. This allows the
use of low-power, slow refresh DRAMs. The VL82C320/VL82C320A controls
all timing in both modes. In all cases, refreshes are staggered to
minimize power supply loading and attendant noise on the VDD and
ground pins. In sleep mode, refresh switches to CAS before RAS refresh
for maximum power savings. the physical banks of DRAM can be
logically reordered through one of the indexed configuration
registers. this DRAM remap option is useful n order to map out bad
DRAM banks allowing continued use of a system until repairs are
convenient. It also allows DRAM bank combinations not in the supported
memory maps to be logically moved into a supported configuration with-
out physically moving memory components.
The 160-lead VL82C331 ISA Bus Controller provides the functions of
DMA, page address register, timer, interrupt control, port B logic,
slot bus refresh address generation, and real-time clock. To avoid
problems with sensitive slot bus add-in cards, the Bus Controller
features "Bus Quiet" mode operation. when no valid slot bus accesses
are occurring, none of the slot bus data, addresses, or control lines
are driven. Built-in "Sleep" mode features work together with System
Controller special features to provide a low-power system idle state
for extension of battery life in portable, laptop, and hand-held
systems. If an interrupt occurs due to an external source or
dedicated, internal programmable timer, the Vus Controller "wakes up"
and resumes normal operation. The DMA channels have been upgraded to
provide a superset of AT functionality by allowing DMA to the entire
23M byte memory range of the TOPCAT 286/386SX chip set. Additional
functionality is provided via DMA wait state, clock and MEMR timing
programmability.
***Configurations:...
***Features:...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
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