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**M1535/D South Bridge ?
***Info:...
***Versions:...
***Features:
o Provides a High Integration Bridge (with Audio, HSP Modem, Super
I/O & Fast IR) between PCI Bus and Peripheral Bus for Notebook or
Mobile Systems
o PCI 3.3V/5V Tolerance Interface
- Supports PCI Master and Slave Interface
- Supports PCI Master and Slave Initiated Termination
- Concurrent PCI Architecture
- PCI spec. 2.2 Compliant
- PCI Power Management Interface spec. 1.1 Compliant
o Provides Steerable PCI Interrupts for PCI Device Plug-and-Play
- Up to 8 PCI Interrupts Routing
- Level to Edge Trigger Transfer
o Enhanced DMA Controller
- Provides 7 Programmable Channels, 4 for 8-bit Data Size, 3 for
16-bit Data Size
- 32-bit Addressability
o Interrupt Controller
- Provides 14 Interrupt Channels
- Independent Programmable Level/Edge Triggered Channels
o Counter/Timers
- Provides 8254 Compatible Timers for System Timer, Refresh
Request, Speaker Output Use
o Distributed DMA Supported
- 7 DMA Channels can be Arbitrarily Programmed as Distributed
Channels
o PC/PCI DMA Supported
- 1 PC/PCI DMA Channel Interface Provided
o Serialized IRQ Supported
- Quiet/Continuous Mode
- Programmable (Default 21) IRQ/DATA Frames
- Programmable START Frame Pulse Width
o Plug-and-Play Supported
- 2 Programmable Chip Select
- 2 Steerable Interrupt Request Lines
o Built-in Keyboard Controller
- Built-in PS2/AT Keyboard and PS2 Mouse Controller
o Supports up to 512 KB ROM Size Decoding
o PMU Features
- Full Support for ACPI and OS Directed Power Management to meet
system requirement of PC98/PC99
- Full Support for Instantly Available PC feature
- CPU SMM Legacy Mode and SMI Feature Supported
- Full Support for Clock Control Functions of both Pentium and
Pentium II CPUs.
- Supports I/O Trap for I/O Restart Feature
- PMU Operation States:
1. G0 State
- On
- Standby Mode
2. G1 State (Suspend Mode 1)
- S1 State (Power On Suspend)
- S3 State (Suspend To RAM)
- S4 State (Suspend To DISK)
3. G2 State (Suspend Mode 2)
- S5 State (Soft-Off)
4. G3 State (Mechanical-Off)
- APM State Detection and Control Logic Supported
- Global and Local Device Power Control Logic
- 10 Monitor Timers: Standby/ APMA ~D/ Global-Display/ HDD A~B/
SIO & Audio/ GPIO.
- 2 Low Battery timers supported.
- Provides System Activity and Display Activity Monitoring,
including
- Video
- Audio
- Hard Disk
- Floppy Disk
- Serial Ports
- Parallel Port
- Keyboard
- 4 Programmable I/O Group
- 2 Programmable Memory Space
- Provides Hot Plugging Events Detection
- Docking Insert
- Multiple External Wakeup Events of Standby Mode (G0)
- Power Button
- Sleep Button
- Modem Ring
- RTC Alarm
- DRQ2
- Resume Events detected Wake Up from Suspend Mode (G1, G2)
- 9 resume events supported.
- Power Button
- Sleep Button
- RTC Alarm
- PCI PMEJ Signal
- Modem Ring
- USB Events
- AC’97
- Hotkey KBD & MS
- IRQ 1 & 12
- CLKRUN# Function Supported for PCI Mobile Design Guide Ver1.1
- Thermal Alarm Supported
- Clock Generator Control Logic Supported
- CPUCLK Stop Control
- PCICLK Stop Control
- L2 Cache Power Down Control Logic Supported
- Up to 25 Run Time Events Supported (included 8 Extended Run Time
Events).
- Up to 12 General Purpose Input Signals, Up to 1 5 General
Purpose Output Signals and up to 30 General Purpose Input/Output
Signals
- 16 Extended General Purpose Input Signals, 16 Extended General
Purpose Output Signals, and 8 Extended Run Time Events
supported.
- All Registers Readable/Restorable for Proper Resume from Suspend
State
- Hotkey for Power on Button Function through Keyboard or Mouse
- Supports Power Loss Recovery
- Watch Dog Timer for
- Set a Bit in Register
- Generate an SMI#/SCI/NMI/INIT
- Generate System Reset
o Built-in PCI IDE Controller
- Supports Ultra DMA Mode Transfers up to Mode 4 Timing (33/66
Mbps)
- Supports PIO Modes up to Mode 4 Timings, and Multiword DMA Mode
0,1,2 with Independent Timing of up to 4 Drives
- Integrated 16 x 32-bit Read Ahead & Posted Write Buffers for
each channel (Total: 32 DWords)
- Dedicated Pins of ATA Interface for each Channel
- Supports Tri-state IDE Signals for Swap Bay
- Supports Command Queue IDE enhancement
o USB Interface
- One Root Hub with four USB Ports Based on OpenHCI 1.0a
Specification
- Supports FS (12Mbits/sec) and LS (1.5Mbits/sec) Serial Transfer
- Supports Legacy Keyboard and Mouse Software with USB-based
Keyboard and Mouse
o SMBus Interface
- System Management Bus Interface Meets the V1.0 Specification
- SMBALERT# Support
- I2C protocol Support
o Hotkey for Power on Button Function through Keyboard
o Super I/O Interface
- Supports Windows Plug-and-Play
- Supports 2 Serial/ 1 Parallel/ FDC Functions
- Supports 16-bit Address Decoder
- 2.88 MB (Formatted) Floppy Disk Controller
- Software Compatible with 82077 and Supports 16-byte Data FIFOs
- High Performance Internal Data Separator
- Supports Standard 1 Mbps/ 500 Kbps/ 300 Kbps/ 250 Kbps Data
Transfer Rate
- Supports 3 modes of 3.5“ FDD ( 720KB / 1.2 MB / 1.44 MB )
- Swappable Drives A and B
- Programmable 7-bit I/O Base Address
- Various Mode Parallel Port
- Supports ECP/ EPP / PS/2 / SPP and 1284 Compliance
- Standard Mode
- Programmable 8-bit I/O Base Address
- Multiplexing of FDC Signals through Parallel Port Pins
- 12 IRQ Channel Options
- 4 8-bit DMA Channel Options
- IBM PC/XT, PC/AT and PS/2 Compatible Bi-directional Parallel
Port
- Enhanced Mode
- Enhanced Parallel Port (EPP) Compatible
- EPP is Compatible with EPP1.9 (IEEE 1284 Compliant ), also
supports EPP1.7 of Xircom Specification
- High Speed Mode
- Microsoft and Hewlett Packard Extended Capabilities Port
(ECP) Compatible
- IEEE1284 Compatible ECP
- Includes Protection Circuit against damage caused when
printer is powered up, or operated at higher voltages
- Serial Ports
- Three High Performance 16450/16550 Compatible UARTs with
Send/Receive 16-byte FIFOs
- Programmable Baud Rate Generator
- Wireless Communications
- Dedicated pins and COM Port for Infrared Transmission
- Supports IrDA 1.0 (SIR) and IrDA 1.1 (MIR and FIR)
- Supports Sharp-IR
- MIDI (Musical Instrument Digital Interface) Compatible
- High Performance Power Management for FDC, UART and Parallel
Port
- Option between Programmable 7-bit I/O Base Addresses, 12 IRQs,
and 4 DMA Channels for each Device
o Audio System
- Fully Plug-and-Play PCI controller and software
- PCI 2.2 compliant bus master optimized for multiple stream
operation
- On-chip per voice cache minimizes PCI bandwidth
- Hardware multi-channel digital mixer
- 32 voices polyphony wavetable synthesizer supports all
combinations of stereo/mono, 8-/16-bits, and signed/unsigned
samples.
- Per channel for wavetable synthesis with envelop, pitch shift,
tremolo and vibrato
- DLS1-compliant Downloadable Samples support
- DirectMusic with unlimited downloadable samples in system memory
- Legacy game audio with SoundBlaster Pro/16 compatibility
- Legacy game FM and wave table synthesis supported
- MPU-401 compatible MIDI I/O with FIFO
- AC97 2.1 support with full duplex, independent sample rate
converter for recording and playback
- On-chip sample rate converter ensures all internal operation at
48KHz
- High precision internal 26 bit digital mixer with 20 bit digital
audio output
- Microsoft WDM streaming architecture compliant and "Re-routable
endpoint" support
- 32-voices DirectSound channels
- 16-voices DirectSound3D accelerator with IID, ITD and Doppler
effect on 3D positional audio buffers
- DirectSound accelerator with volume, pan and pitch shift control
on streaming or static buffers
- DirectInput support with digital enhanced game port enables an
analog joystick to emulate digital joystick performance using
DirectInput driver. This eliminates up to 12% CPU overhead
wasted on joystick polling.
- DirectX timer for video/audio synchronization
- Hardware digital volume control
o Software Modem Interface
- The M1535 will provide the AC’97 2.1 compliant digital
controller interface for third parties (such as the AMC Codec’s
vendor) to enable the software modem solution.
- 4 separate telephony bus master channels. One for modem output,
one for mode minput, one for handset input, and one for handset
output.
- AC’97 2.1 Modem variable sample rate support for "On Demand"
sample transport scheme.
- AC’97 2.1 GPIO pin status and control support.
- Power Management and wake-up event support
- Caller ID string transmission via AC-link support
o 352-pin (27mmx27mm) BGA Package
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97
***Info:...
***Configurations:...
***Features:
o Support Intel Pentium CPU and other compatible CPU host bus
at 50/55/60/66/75 MHz
o Support CPU with MMX feature
o Support the Pipelined Address Mode of Pentium CPU
o Support the Full 64-bit Pentium Processor data Bus
o Meet PC97 Requirements
o Integrated Second Level (L2) Cache Controller
- Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty RAM
- Support Pipelined Burst SRAM
- Support 256 KBytes and 512 KBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
o Integrated DRAM Controller
- Support 6 RAS lines (3 Banks) of FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 384Mbytes of main memory
- Support Cacheable DRAM Sizes up to 128 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support 3.3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Support 32 bits/64 bits mixed mode configuration
- Support Concurrent Write Back
- Support CAS before RAS Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current.
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Support FPM DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 6-1-1-1(-2-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Support 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Meet ACPI Requirements
- Support Both ACPI and Legacy PMU
- Support Suspend to Disk
- Support SMM Mode of CPU
- Support CPU Stop Clock
- Support Power Button for ACPI function
- Support Automatic Power Control for system power off function
- Support Modem Ring-in, RTC Alarm Wake up
- Support Thermal Detection
- Support GPIOs, and GPOs for External Devices Control
- Support Programmable Chip Select
o Provides High Performance PCI Arbiter.
- Support up to 4 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI.
o Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep,
Always Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always
Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Integrated Video/Graphics Accelerator
- Support 32-bit PCI local bus standard revision 2.1
- Built-in an enhanced 64-bit BITBLT graphics engine
- Support tightly coupled host interface to VGA to speed up GUI
performance and the video playback frame rate
- Support direct access to video memory to speed up GUI
performance and the video playback frame rate
- Shared System Memory Area 0.5MB, 1MB, 1.5MB, 2MB, 2.5MB, 3MB,
3.5MB, 4MB
- Built-in programmable 24-bit true-color RAMDAC with reference-
voltage generator
- Built-in dual-clock generator
- Built-in monitor-sense circuit
- Built-in Phillips SAA7110/SAA7111, Brooktree Bt815/817/819A
(8 -bit SPI mode 1,2) video decoder interface
- Built-in Standard feature connector logic support
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
- Support Distributed DMA
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
- Support Serial IRQ
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Support PS/2 Mouse interface
- Support Hot Key "Wake-up" Function
- Capable of Enable/Disable Internal KBC and PS2 Mouse
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
- Built-in up to one Month Alarm for ACPI
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant
Controller
- Support PCI Bus Mastering
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 Dword FIFO for PCI Burst Transfers.
o Universal Serial Bus Host Controller
- OpenHCI Host Controller with Root Hub
- Two USB ports
- Support Legacy Devices
- Support Over Current Detection
o Support I2C serial Bus
o Support the Reroutibility of the four PCI Interrupts
o Support 2Mb Flash ROM Interface
o Support Signature Analysis for automatic test for VGA controller
o Support NAND Tree for ball connectivity testing
o 553-Balls BGA Package
o 0.35μm 3.3V Technology
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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