[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
**M6117          386SX Single Chip PC                              <97
***Notes:...
***Info:...
***Versions:...
***Features:
o   Static Intel 386SX compatible Core 
    - Operating Power Supply  5.0V 
    - Operating frequency 25Mhz to 40Mhz 
o   Memory Controller
    - Supports EDO DRAM 
    - Supports on board memory size up to 16M bytes for 386SX or 64M 
      bytes upgrade system using 256K, 512K, 1M, 4M or 16M SIMMs 
    - Supports up to 4-bank DRAM interface 
    - Page interleave DRAM access for FP mode 
    - Programmable shadow RAM from A to B segment in 128K byte and C 
      to F segment in 32K byte unit 
    - Provides "RAS only" refresh or "CAS before RAS” refresh types 
    - Parity generation and checking 
o   Peripheral Interface 
    - Includes 2 cascaded 8237 DMA controllers 
    - Includes 1 74612 memory mapper 
    - Includes 2 cascaded 8259 interrupt controllers 
    - Includes 1 8254 programming counter 
o   ISA Interface
    - Executes cycles for requests from CPU, DMA and ISA bus master 
    - Assembles or de-assembles data for multiple bus cycle or 
      unmatched data width 
    - Generates refresh signals to ISA slots during DRAM refresh 
      cycles 
o   Built-in RTC 
    - Internal Real Time Clock that provides 128 byte CMOS RAM 
o   Programmable 2 channels chip select 
    - Provide chip select for memory  or I/O device without external 
      address decode random logic 
o   Built-In PS2/AT Keyboard Controller
    - Internal PS2/AT keyboard controller and mouse 
o   PMU interface 
    - Supports CPU SMM mode, SMI feature 
    - Supports APM control 
    - Provides External Suspend mode switch 
    - Provides four (4) system states for power saving (On, Doze, 
      Standby, Suspend) 
    - Supports RTC alarm wake up control 
o   Expandable GPI/O signals
    - Provides sixteen External power control input and output signals 
    - Provides sixteen independent pin for general purpose input and 
      output signals 
o   Watchdog timer 
    - When timer times out , a system reset or NMI or IRQ happens 
o   IDE interface
    - Provides a decoder for external IDE connection
o   Packaging 
    - 208-pin PQFP package

**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0   c:Jul89
***Notes:...
***Info:
The GC103 is a companion chip  to the GC101/102 AT chip set. Replacing
the GC102  in its Address Buffer  mode, this chip adds  logic to fully
implement LIM, EMS  4.0.  This device expands the  capabilities of the
GC101/102  chip set.   It adds  support for  up to  8MB of  memory and
Shadow RAM for systems  and video BIOS. The register-intensive design,
combined  with the  use of  system memory,  offers extremely  high EMS
throughput compared with EMS  systems using fewer mapping registers or
expansion  memory. The  GC103 contains  a chip  mapping  register that
allows  EMS  to operate  at  full  system  speed without  adding  wait
states. With 2 sets of  32 EMS registers context switching in hardware
as well as software is supported.

The GC103 provides address buffering  for the expansion bus, local I/O
bus, and the  system board DRAM.  Address ,  DMA, and Refresh controls
are  included  in the  GC103.  The  chip  integrates additional  logic
previously implemented discretely in  the GC101/102 board design. This
device is packaged in a 160 pin quad flatpack.

***Configurations:...
***Features:...
**GCK113        80386 AT Compatible Chip Set                   c:oct89...
**GCK181        Universal PS/2 Chip Set                        c:Mar89...
**HT11          Single 286 AT Chip [no datasheet]               <Aug90...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...