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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
**Later P-Pro/II/III/Celeron
***Notes (Unverified Information!):...
***VT82C691/2BX Apollo Pro & Pro II May 98...
***VT82C693 Apollo Pro+ Dec 98...
***VT82C693A Apollo Pro 133 Jul 99...
***VT82C694X/MP/Z/A Apollo Pro 133A, 133+ & 133Z Oct 99
Chips:
[VT82C694X or VT82C694MP] (North Bridge)
[VT82C596B or VT82C686A/B]] (South Bridge)
CPUs: Single or Dual (VT82C694MP only) P-III, P-II, Celeron
Bus Speed: 66/100/133 MHz
DRAM Types: PC100/PC133 SDRAM, Reg SDRAM ESDRAM VCSDRAM
Memory bus: 66/100/133 MHz
Max Mem: 2 GB, rev CE and later possibly 4GB
ECC/Parity: Both
PCI Bus: 2.1
AGP speed: 4×
Only 6 banks can be used with 133 MHz RAM, 8 for 100Mhz. Reg RAM may
be different.
Apollo Pro 133Z [VT82C694Z] is an ASUS OEM version of the VT82C694X. It
could be pin compatible with the VT8605 (PM133).
Apollo Pro 133+ Seems to be the same as the 133A.
VT82C694A is an early internal (to VIA) name for the VT82C694X.
***VT82C694T Apollo Pro 133T...
***VT8601 PN133 (ProSavage) (mobile)...
***VT8601/A/T PM601, PLE133, PLE266 & PLE133T (ProMedia)...
***VT8604/T PL133 & PL133T (ProSavage)...
***VT8605/6 PM133 & PM133T (ProMedia-II), (ProSavage)...
***VT8607/8 PM266 & PM266T (ProSavageDDR)...
***VT8613 PN266T (mobile)...
***VT8633 Apollo Pro 266 Sep 00...
***VT8653 Apollo Pro 266T & PX-266...
***VT8622/23 CLE266 (mobile)...
***VT???? CM400 Jan 04...
***Others:...
**Later AMD...
**Other...
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