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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97
***Info:...
***Versions:...
***Features:
o Inter-operable with VIA and other Host-to-PCI Bridges
- Combine with VT82C597 for a complete 66MHz Socket-7 PCI / AGP /
ISA system (Apollo VP3)
- Combine with VT82C598 for a complete 66 / 75 / 83 / 100MHz
Socket-7 PCI / AGP / ISA system (Apollo MVP3)
- Combine with VT82C691 for a complete Socket-8 or Slot-1 PCI /
ISA system (Apollo Pro)
- Inter-operable with Intel or other Host-to-PCI bridges for a
complete PC97 compliant PCI / AGP / ISA system
o Pin-compatible upgrade for PIIX4 for existing designs
o PC98 Compliant PCI to ISA Bridge
- Integrated ISA Bus Controller with integrated DMA, timer, and
interrupt controller
- Integrated Keyboard Controller with PS2 mouse support
- Integrated DS12885-style Real Time Clock with extended 256 byte
CMOS RAM and Day/Month Alarm for ACPI
- Integrated USB Controller with root hub and two function ports
- Integrated UltraDMA-33 master mode EIDE controller with enhanced
PCI bus commands
- PCI-2.1 compliant with delay transaction
- Eight double-word line buffer between PCI and ISA bus
- One level of PCI to ISA post-write buffer
- Supports type F DMA transfers
- Distributed DMA support for ISA legacy DMA across the PCI bus
- Sideband signal support for PC/PCI and serial interrupt for
docking and non-docking applications
- Fast reset and Gate A20 operation
- Edge trigger or level sensitive interrupt
- Flash EPROM, 2Mb EPROM and combined BIOS support
- Supports positive and subtractive decoding
- Supports external APIC interface for symmetrical multiprocessor
configurations
o UltraDMA-33 Master Mode PCI EIDE Controller
- Dual channel master mode PCI supporting four Enhanced IDE
devices
- Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA
mode 2 drives, and UltraDMA-33 interface
- Thirty-two levels (doublewords) of prefetch and write buffers
- Dual DMA engine for concurrent dual channel operation
- Bus master programming interface for SFF-8038i rev.1.0 and
Windows-95 compliant
- Full scatter gather capability
- Support ATAPI compliant devices including DVD devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
- Supports glue-less “Swap-Bay” option with full electrical
isolation
o Universal Serial Bus Controller
- USB v.1.0 and Intel Universal HCI v.1.1 compatible
- Eighteen level (doublewords) data FIFO with full scatter and
gather capability
- Root hub and two function ports
- Integrated physical layer transceivers with over-current
detection status on USB inputs
- Legacy keyboard and PS/2 mouse support
o System Management Bus Interface
- Host interface for processor communications
- Slave interface for external SMBus masters
o Sophisticated PC97-Compatible Mobile Power Management
- Supports both ACPI (Advanced Configuration and Power Interface)
and legacy (APM) power management
- ACPI v1.0 Compliant
- APM v1.2 Compliant
- CPU clock throttling and clock stop control for complete ACPI C0
to C3 state support
- PCI bus clock run and PCI/CPU clock generator stop control
- Supports multiple system suspend types: power-on suspends with
flexible CPU/PCI bus reset options, suspend to DRAM, and suspend
to disk (soft-off), all with hardware automatic wake-up
- Multiple suspend power plane controls and suspend status
indicators
- One idle timer, one peripheral timer and one general purpose
timer, plus 24/32-bit ACPI compliant timer
- Normal, doze, sleep, suspend and conserve modes
- Global and local device power control
- System event monitoring with two event classes
- Primary and secondary interrupt differentiation for individual
channels
- Dedicated input pins for power and sleep buttons, external modem
ring indicator, and notebook lid open/close for system wake-up
- Up to 22 general purpose input ports and 31 output ports
- Multiple internal and external SMI sources for flexible power
management models
- Two programmable chip selects and one microcontroller chip
select
- Enhanced integrated real time clock (RTC) with date alarm, month
alarm, and century field
- Thermal alarm support
- Cache SRAM power-down control
- Hot docking support
- I/O pad leakage control
o Plug and Play Controller
- PCI interrupts steerable to any interrupt channel
- Three steerable interrupt channels for on-board plug and play
devices
- Microsoft Windows 95TM and plug and play BIOS compliant
o Built-in NAND-tree pin scan test capability
o 0.5u, 3.3V, low power CMOS process
o Single chip 324 pin BGA
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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