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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97
***Info:...
***Configurations:...
***Features:...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94
***Info:...
***Versions:
VT82C505

***Features:
o   VL to PCI Bridge
    - Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based 
      PCI/VL/ISA Green-PC systems
    - Combined with VT82C530MV chip set for Pentium/P54C/M1 based 
      PCI/VL/ISA Green-PC Systems
o   Sophisticated Bridging Capabilities
    - Supports PCI master to PCI slave cycles
    - Supports PCI master to VL bus slave, system memory and ISA 
      slave cycles
    - Supports VL master including CPU to PCI slave cycles
    - Supports ISA master to VL or PCI slave cycles
    - Supports multiple accelerated decoding schemes from VL master 
      including CPU to PCI and ISA slaves
    - Supports CPUs with write-back level-one cache
    - Concurrent CPU and PCI operation
    - 4 level of CPU/VL to PCI post write buffers
    - Automatic detection of data streaming burst cycles from CPU/VL 
      to PCI bus
    - 4 level of post write buffers from PCI master to VL slave, 
      system memory and ISA slaves
    - 4 level of prefetch buffers from system memory for access by PCI 
      masters
    - Bursting capability for both PCI and CPU/VL bus
o   Intelligent PCI Interface
    - PCI 2.0 compliant
    - Synchronous or divide-by-two CPU clock
    - Hidden arbitration for up to four PCI masters
    - Supports PCI preemption and time-out function
    - Supports PCI master and slave initiated abort mechanism
    - Supports PCI lock function
    - Supports data parity generation for PCI master read cycles
    - Supports data parity checking for PCI master write cycles
    - Supports parity error and system error reporting on the PCI bus
    - Supports PCI configuration cycles
    - Interrupt steering and conversion to edge triggering for ISA 
      compatibility
o   PCI Compliant IO Characteristics
o   0.8um high speed and low power CMOS process
o   160pin PQFP package

**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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