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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*Unresearched:...
*VIA...
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94
***Info:...
***Versions:...
***Features:
o   VL to PCI Bridge
    - Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based 
      PCI/VL/ISA Green-PC systems
    - Combined with VT82C530MV chip set for Pentium/P54C/M1 based 
      PCI/VL/ISA Green-PC Systems
o   Sophisticated Bridging Capabilities
    - Supports PCI master to PCI slave cycles
    - Supports PCI master to VL bus slave, system memory and ISA 
      slave cycles
    - Supports VL master including CPU to PCI slave cycles
    - Supports ISA master to VL or PCI slave cycles
    - Supports multiple accelerated decoding schemes from VL master 
      including CPU to PCI and ISA slaves
    - Supports CPUs with write-back level-one cache
    - Concurrent CPU and PCI operation
    - 4 level of CPU/VL to PCI post write buffers
    - Automatic detection of data streaming burst cycles from CPU/VL 
      to PCI bus
    - 4 level of post write buffers from PCI master to VL slave, 
      system memory and ISA slaves
    - 4 level of prefetch buffers from system memory for access by PCI 
      masters
    - Bursting capability for both PCI and CPU/VL bus
o   Intelligent PCI Interface
    - PCI 2.0 compliant
    - Synchronous or divide-by-two CPU clock
    - Hidden arbitration for up to four PCI masters
    - Supports PCI preemption and time-out function
    - Supports PCI master and slave initiated abort mechanism
    - Supports PCI lock function
    - Supports data parity generation for PCI master read cycles
    - Supports data parity checking for PCI master write cycles
    - Supports parity error and system error reporting on the PCI bus
    - Supports PCI configuration cycles
    - Interrupt steering and conversion to edge triggering for ISA 
      compatibility
o   PCI Compliant IO Characteristics
o   0.8um high speed and low power CMOS process
o   160pin PQFP package

**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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