[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99
***Notes:...
***Info & Features:...
***Configurations:...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:
Date source: TimelineDateSort7_05.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**

>*  Datasheet dated Oct'93
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

This  chip was  used on  the Pentium  66MHz CPU  complexes of  Intel's
Xpress platform.   Specifically the  BXCPUPENT66 (Single  66MHz, eight
82491s) and BXCPU2XPENT (Dual 66 MHz,  eight 82491s). Also found on P5
60/66MHz CPU complexes of IBM 9595/PC Server 300/500 systems.

***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...