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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX  CPU-Cache Chip Set provides a high performance
solution  for  servers  and  high-end desktop  systems.   This  binary
compatible solution  has been optimized  to provide 50 MHz,  zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with  the 82495DX/82490DX cache  subsystem. It delivers
integer  performance of  41 V1.1  Dhrystone  MlPs and  a SPEC  integer
rating  of  27.9.  The  cache  subsystem  features  the 82495DX  Cache
Controller and the 82490DX Dual  Ported Data RAM.  Dual ported buffers
and registers  of the  82490DX allow the  82495DX Cache  Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.

The CPU-Cache Chip Set offers  many features that are ideal for multi-
processor  based systems.  The  Write-Back feature  provides efficient
memory  bus utilization  by reducing  bus traffic  through eliminating
unnecessary  writes  to main  memory.   The  CPU-Cache  chip set  also
supports MESI protocol and monitors  the memory bus to guarantee cache
coherency.

The 50  MHz Intel486  DX CPU and  82495DX/82490DX Cache  subsystem are
produced on  Intel's latest CHMOS  V process which  features submicron
technology and triple layer metal.

3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip  set provides a tightly coupled processing
engine  based on  the Intel486  microprocessor and  a  cache subsystem
comprised of  the 82495DX cache controller and  multiple 82490DX cache
components.   Figure 3.1  [see datasheet]  diagrams the  basic config-
uration.

The cache subsystem provides a  gateway between the CPU and the memory
bus. All CPU accesses that  can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic.  As a result, the cache
chip  set  reduces memory  bus  bandwidth  to  both increase  Intel486
processor  performance and  support efficient  multiprocessor systems.
The  cache subsystem also  decouples the  CPU from  the memory  bus to
provide  zero-wait-state  operation at  high  clock frequencies  while
allowing relatively slow and inexpensive memories.

The  CPU-cache chip  set  prevents latency  and bandwidth  bottlenecks
across  a variety  of  uniprocessor and  multiprocessor designs.   The
processor’s  on-chip cache  supports  a  very wide  CPU  data bus  and
high-speed data  movement. The second-level cache  greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.

3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks: 

3.2.1 CPU
The chip  set includes a  special version of the  Intel486DX micropro-
cessor at  50 MHz.  The Intel486DX Microprocessor  Data Sheet provides
complete component specifications.

3.2.2 CACHE CONTROLLER
The 82495DX cache controller is  the main control element for the chip
set. providing  tags and line  states. and determining cache  hits and
misses. The 82495DX executes all  CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).

The 82495DX  controls the data  paths of the 82490DX  cache components
for cache hits and misses and furnishes the CPU with needed data.  The
controller  dynamically adds  wait  states as  needed  using the  most
recently used (MRU) prediction algorithm.

The 82495DX also performs memory bus snoop operations in shared memory
systems  and drives  the  cycle address  and  other attributes  during
memory bus accesses. Figure  3.2 [see datasheet] diagrams the 82495DX.

3.2.3 CACHE SRAM

Multiple  82490DX cache  components provide  the cache  SRAM  and data
path. Each component  includes the latches, muxes and  logic needed to
work in lock  step with the 82495DX to efficiently  serve both hit and
miss  accesses.  The 82490DX  components take  full advantage  of VLSI
silicon   flexibility   to  exceed   the   capabilities  of   discrete
implementations.  The  82490DX components support  zero-wait-state hit
accesses  and  concurrent  CPU  and  memory  bus  accesses,  and  they
replicate MRU  bits for autonomous  way prediction. During  memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.

3.3 Secondary Cache Features

The 82495DX  cache controller and  82490DX cache components  provide a
unified, software  transparent secondary  data and  instruction cache.
The cache enables  a highspeed processor core  that provides efficient
performance even when paired with a significantly slower memory bus.

The secondary  cache interprets  CPU bus cycles  and can  service most
memory read and  write cycles without accessing main  memory.  I/O and
other special cycles are passed directly to the memory bus.  The cache
has a dual-port  structure that permits concurrent CPU  and memory bus
operation.

The 82495DX  cache controller  contains the 8K  tag entries  and logic
needed to support a cache as  large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are  used to create caches ranging from 128K
to 256K, with or without data parity.

The  MBC provides  logic  needed  to interface  the  CPU, 82495DX  and
82490DX  to the  memory  bus.   Because the  MBC  also affects  system
performance.  its design can be the basis of product differentiation.

***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*VIA...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98
***Notes:...
***info:
The  Apollo MVP4  is  a PC  Socket-7  system logic  North Bridge  with
integrated 2D  / 3D Graphics  accelerator.  The core logic  portion of
the chip is  based on the popular 100MHz VIA  Apollo MVP3 chipset with
enhanced features  and graphics accelerator based  on the Cyber9398DVD
from Trident  Microsystems, Inc.  The  combination of the  two leading
edge  technologies   provides  a  stable,   cost-effective,  and  high
performance solution for personal computers, embedded systems, set-top
boxes and  others.  As  shown in Figure  1 [see datasheet]  below, the
Apollo MVP4 will interface to:

o Socket 7 CPU (66 – 100 MHz)
o L2 Cache RAM & Tag
o SDRAM Memory Interface
o PCI Bus (30 - 33 MHz)
o Analog RGB Monitor with DDC
o DFP / Digital Monitor Interface (TMDS)
o Video Capture / Playback CODECs

Apollo MVP4 Core Logic Overview
The Apollo  MVP4 –  System Media Accelerated  North Bridge (SMA)  is a
high performance, cost-effective and energy efficient solution for the
implementation  of Integrated  2D/3D  Graphics -  PCI  - ISA  personal
computer  systems from  66 MHz  to 100  MHz based  on  64-bit Socket-7
(Intel Pentium and Pentium MMX; AMD K6 and K6-2; Cyrix / National 6x86
/ 6x86MX, IDT / Centaur C6/WinChip), and Rise MP6 processors.

The Apollo  MVP4 controller provides superior  performance between the
integrated  2D/3D Graphics  Engine, CPU,  optional  synchronous cache,
DRAM,  and PCI bus  with pipelined,  burst, and  concurrent operation.
For  L2-Cache  solutions  using  pipelined  burst  synchronous  SRAMs,
3-1-1-1-1-1-1-1  timing  can  be  achieved  for both  read  and  write
transactions at 100 MHz.  Tag timing is specially optimized internally
(less  than 4 nsec  setup time)  to allow  implementation of  L2 cache
using an external tag for t  he most flexible cache organization (0K /
256K / 512K / 1M /  2M).  Four cache lines (16 quadwords) of CPU/cache
to  DRAM  write  buffers  with concurrent  write-back  capability  are
included on chip to speed up cache read and write miss cycles.

The Apollo  MVP4 supports six  banks of DRAMs  up to 768MB.   The DRAM
controller  supports  standard Fast  Page  Mode  (FP) DRAM,  EDO-DRAM,
Synchronous DRAM  (SDRAM), and Virtual  Channel Synchronous DRAM  in a
flexible mix  / match manner.   The Synchronous DRAM  interface allows
zero wait state bursting between the  DRAM and the data buffers at 100
MHz.  The six banks of DRAM can be composed of an arbitrary mixture of
1M / 2M  / 4M / 8M  / 16MxN DRAMs.  The DRAM  controller also supports
optional ECC (single-bit error  correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis.   The  DRAM Controller  can  run at  either  the  host CPU  bus
frequency (66  / 100 MHz) or  at the PC100 memory  frequency (100 MHz)
with  built-in deskew  PLL  timing control.   With  the advanced  DRAM
controller,  the  Apollo  MVP4   allows  implementation  of  the  most
flexible, reliable, and high-performance DRAM interface.

The  Apollo MVP4  also  supports  full AGP  v2.0  capability with  the
internal 2D/3D Graphics Engine for maximum software compatibility.  An
eight level request  queue plus a four level  post-write request queue
with thirty-two  and sixteen quadwords  of read and write  data FIFO’s
respectively   are  included   for  deep   pipelined  and   split  AGP
transactions.   A  single-level  GART  TLB with  16  full  associative
entries and  flexible CPU/AGP/PCI  remapping control is  also provided
for  operation  under  protected  mode operating  environments.   Both
Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.

The Apollo MVP4 supports one 32-bit  3.3 / 5V system bus (PCI) that is
synchronous  /  pseudo-synchronous to  the  CPU  bus.   The chip  also
contains a built-in AGP bus  -to- PCI bus bridge to allow simultaneous
concurrent  operations  on each  bus.   Five  levels (doublewords)  of
posted write buffers are included  to allow for concurrent CPU and PCI
operation.  For PCI master operation, forty-eight levels (doublewords)
of posted  write buffers and sixteen levels  (doublewords) of prefetch
buffers are  included for concurrent PCI bus  and DRAM/cache accesses.
The   chip  also   supports  enhanced   PCI  bus   commands   such  as
Memory-Read-Line,   Memory-Read-Multiple,   and   Memory-Write-Invalid
commands to  minimize snoop overhead.  In  addition, advanced features
are  supported such  as snoop  ahead, snoop  filtering,  L1 write-back
forward to  PCI master, and L1  write-back merged with  PCI post write
buffers  to minimize  PCI master  read latency  and  DRAM utilization.
Delayed transaction  and read caching mechanisms  are also implemented
for further improvement of overall system performance.

The Apollo MVP4 provides independent  clock stop control for the CPU /
SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of
the SDRAM.  A separate suspend-well plane is implemented for the SDRAM
control  signals  for  Suspend-to-DRAM  operation.  Coupled  with  the
324-pin Ball Grid Array VIA VT82C596B south bridge chip, a complete PC
main board can be implemented with no external TTLs.

The Apollo MVP4 controller  coupled with VIA’s highly integrated south
bridge,  the   VT82C686A,  is  ideal  for   high  performance,  energy
efficient,  and  highly integrated  computer  systems.  The  VT82C686A
supports a PCI-to-ISA bus  controller, four USB ports, dual bus-master
IDE  with UltraDMA33/66,  AC97  basic digital  audio, system  hardware
monitoring, and integrated "Super-I/O" functionality.
***Configurations:...
***Features:...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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