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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97
***Notes:...
***Info:
The Apollo MVP3 is a high performance, cost-effective and energy
efficient chip set for the implementation of AGP / PCI / ISA desktop
and notebook personal computer systems from 66 MHz to 100 MHz based on
64-bit Socket-7 (Intel Pentium and Pentium MMX; AMD K6; Cyrix / IBM 6
x86 / 6x86MX, and IDT / Centaur C6/WinChip) super-scalar processors.
The Apollo-MVP3 chip set consists of the VT82C598MVP system controller
(476 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
system controller provides superior performance between the CPU,
optional synchronous cache, DRAM, AGP bus, and PCI bus with pipelined,
burst, and concurrent operation. For pipelined burst synchronous
SRAMs, 3-1-1-1-1-1-1-1 timing can be achieved for both read and write
transactions at 100 MHz. Tag timing is specially optimized internally
( less than 4 nsec setup time) to allow implementation of L2 cache
using an external tag for the most flexible cache organization (0K /
256K / 512K / 1M / 2M). Four cache lines (16 quadwords) of CPU/cache
to DRAM write buffers with concurrent write-back capability are
included on chip to speed up cache read and write miss cycles.
The VT82C598MVP supports six banks of DRAMs up to 768MB. The DRAM
controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM, and
Synchronous DRAM (SDRAM) in a flexible mix / match manner. The
Synchronous DRAM interface allows zero wait state bursting between the
DRAM and the data buffers at 100 MHz. The six banks of DRAM can be
composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs.
The DRAM controller also supports optional ECC (single-bit error
correction and multi-bit detection) or EC (error checking) capability
separately selectable on a bank-by-bank basis. The DRAM Controller
can run at either the host CPU bus frequency (66 / 75 / 83 / 100 MHz)
or at the AGP bus frequency (66 MHz) with built-in deskew DLL timing
control. The VT82C598MVP allows implementation of the most flexible,
reliable, and high-performance DRAM interface.
The VT82C598MVP also supports AGP v2.0 compatibility for maximum bus
utilization including 2x mode transfers, SBA (SideBand Addressing),
Flush/Fence commands, and pipelined grants. An eight level request
queue plus a four level post-write request queue with thirty-two and
sixteen quadwords of read and write data FIFO's respectively are
included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible
CPU/AGP/PCI remapping control is also provided for operation under
protected mode operating environments. Both Windows-95 VXD and
Windows-98 / NT5 miniport drivers are supported for interoperability
with major AGP-based 3D and DVD-capable multimedia accelerators.
The VT82C598MVP supports two 32-bit 3.3 / 5V system buses (one AGP and
one PCI) that are synchronous / pseudo-synchronous to the CPU bus.
The chip also contains a built-in bus-to-bus bridge to allow
simultaneous concurrent operations on each bus. Five levels
(doublewords) of post write buffers are included to allow for
concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen
levels (doublewords) of prefetch buffers are included for concurrent
PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI
bus commands such as Memory-Read-Line, Memory-Read-Multiple and
Memory-Write-Invalid commands to minimize snoop overhead. In
addition, advanced features are supported such as snoop ahead, snoop
filtering, L1 write-back forward to PCI master, and L1 write-back
merged with PCI post write buffers to minimize PCI master read latency
and DRAM utilization. Delay transaction and read caching mechanisms
are also implemented for further improvement of overall system
performance.
The VT82C586B PCI to ISA bridge supports four levels (doublewords) of
line buffers, type F DMA transfers and delay transaction to allow
efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C586B
also includes an integrated keyboard controller with PS2 mouse
support, integrated DS12885 style real time clock with extended 256
byte CMOS RAM, integrated master mode enhanced IDE controller with
full scatter and gather capability and extension to UltraDMA-33 /
ATA-33 for 33MB/sec transfer rate, integrated USB interface with root
hub and two function ports with built-in physical layer transceivers,
Distributed DMA support, and OnNow / ACPI compliant advanced
configuration and power management interface. Using the low-cost
208-pin PQFP-packaged VT82C586B south bridge chip, a complete main
board can be implemented with only four TTLs.
For sophisticated notebook implementations, the VT82C598MVP provides
independent clock stop control for the CPU / SDRAM, PCI, and AGP buses
and Dynamic CKE control for powering down of the SDRAM. A separate
suspend-well plane is implemented for the SDRAM control signals for
Suspend-to-DRAM operation. Coupled with the 324-pin Ball Grid Array
VT82C596 "Mobile South" chip, a complete notebook PC main board can be
implemented with no external TTLs.
The Apollo MVP3 chipset is ideal for high performance, high quality,
high energy efficient and high integration desktop and notebook AGP /
PCI / ISA computer systems.
***Configurations:...
***Features:...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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