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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486DX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct Mapped Cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page-hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
- Programmable wait states for DRAM reads and writes
- Enhanced DRAM configuration map
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
- Programmable wake-up events through hardware, software and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
- One programmable GREEN event timer
o ISA interface:
- 100% IBM PC/AT ISA compatible
- Integrates DMA, timer and interrupt controllers
- Optional PS/2 style IRQ1 and 12 latching
o VESA VL interface:
- Conforms to the VESA v2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features:
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high-speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97
***Notes:...
***Info:
The VT82C580VPX Apollo-VPX is a high performance, cost-effective and
energy efficient chip set for implementation of PCI / ISA desktop and
notebook personal computer systems based on 64-bit P54C/
Pentium/K5/K6/M1 super-scalar processors. The CPU / cache connection
is supported using an "asynchronous" interface up to 75Mhz CPU
external bus speed (with CPU internal speed up to 200Mhz and above),
with CPUs such as the "P200+" processors from Cyrix / IBM
Microelectronics. The "asynchronous" interface allows the processor
external bus frequency to be increased above 66MHz while still
allowing the PCI bus to run at the specified top frequency of 33MHz.
The chipset also supports CPU external bus speeds up to 66MHz in
"synchronous" mode, so may also be used in boards designed around the
popular VT82C580VP (Apollo VP) chipset. The 66MHz external bus speed
is used primarily for Intel and AMD processors. The CPU, DRAM and PCI
bus are all independently powered so that each of the bus can be run
at 3.3v or 5v, independently. The ISA bus always runs at 5v.
The VT82C580VPX chip set consists of the VT82C585VPX system
controller, the VT82C586B PCI to ISA bridge, and two instances of the
VT82C587VP data buffers. The VT82C585VPX is the only different
component in a VPX-based system from the chips used in an Apollo VP
system: the same VT82C586B South Bridge chip may be used with all VIA
North Bridge chips (Pentium and PentiumPro-based designs) and the
VT82C587VP Data Buffer is the same chip as is used in Apollo VP
designs.
The CPU bus is minimally loaded with only the CPU, secondary cache and
the chip set. The VT82C587VP data buffers isolate the CPU bus from
the DRAM and PCI bus so that CPU and cache operation may run reliably
at the high frequencies demanded by today's processors. The
VT82C585VPX contains multiple deep FIFOs to allow efficient concurrent
operation and DRAM utilization. The VT82C586B PCI to ISA bridge
includes integrated 206-style IPC (DMA, interrupt controller and
timer), integrated keyboard controller with PS2 mouse support,
integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, ACPI-compatible Power Management subsystem, integrated master
mode enhanced IDE / UltraDMA-33 disk controller with full scatter and
gather capability, and integrated USB (universal serial bus) interface
with root hub and two function ports with built-in physical layer
transceivers (refer to the separate VT82C586B Data Sheet for
additional information). A complete main board can be implemented
with only six TTLs. Refer to Figure 1 [see datasheet] for the system
block diagram.
***Configurations:...
***Features:...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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